ADN4604 SCL fall time problem

Hi, 

Can the customer send the timing diagram of the SCL and the SDA signals? 

The maximum allowed fall time for SCL is around 300ns, which is very close to what the customer's observing on their system (270ns).It may cause misalignment on the timing diagram.

Does the ADN4604 send an ACK bit during the I2C transaction?

Regards,

Mark

Here are scope shots.

in Figure1 for sequential read to he existing CPU

in Figure2 for sequential read to the new CPU, read 0xFF in the 3rd read.

in Fire3 SCL enlarged 

would you give me any suggestion to find the cause of the problem

figure1 for sequential read OK pattern

figure2 for sequential read NG pattern, In the 3rd read, he got 0xFF

fgure3 SCL transition (enlarged)

I have one more question.

Can ADN4604 accept this type of I2C sequential read?

It looks ADN4604 accept the sequential read request from the existing CPU and return the right value.

I wonder if this is really SCL slew rate problem.

what is the definition of SCl tr/tf?  transition time between 0.3*DVCC and 0.7*DVCC? or 0.1*DVCC and 0.9*DVCC?

The rise time and fall time is measured between 30% and 70% of DVDD.

In that case, judging from the waveform, SCL fall time is about 270ns.

why does he fail data read?

Can you confirm with the customer the following to see if the SCL fall time is really the problem:

1. What are the pullup resistor values at the I2C line? Try changing it to also change the rise/fall time.

2. Is there any I2C devices connected at the bus? Try to isolate the ADN4604 and check again.

OK, thank you for your advice.

would you teach me one more thing?

As I explained, he sent me sequential read oscilloscope shot.

But, looks like he does NOT follow the I2C data read sequence in the  datashhet Page25, but executes

like multi-byte readin which he executes step 1 -> 12 and repeat 11,12,11,12...

Does ADN4604 accept his multi-byte data read sequence?

Judging from the scope shot, ADN4604 replied.

After one I2C read, he can read again the same address (start at step 8) or read another address (start at step 2) by sending a repeated start condition to the ADN4604 (SCL high, SDA high).

After one I2C read, he can read again the same address (start at step 8) or read another address (start at step 2) by sending a repeated start condition to the ADN4604 (SCL high, SDA high).