ADN4604 SCL fall time problem

I'm DFAE in Japan.

My customer is changing CPU(I2C master) to the new one and has the SCL fall time problem.

Here is his problem.

The exsiting CPU(I2C master) has about 60ns fall time(0.7xDVCC -> 0.3xDVCC) and

he does NOT have any problem during data read.

When he tested the new CPU whose SCL fall time is about 270ns(max), he had sequential data read problem roughly once in ten times.

The only difference between the existing CPU and new one is SCL fall time.

he also said he does NOT have this problem for ADN6405.

Would you inform us if this is the potential problem in ADN6404?

why does NOT problem happen for ADN4605?