ADN4600 SEU data

I'm looking for soft error rates in FIT/Mb caused by single event upsets (SEUs) affecting memory cells used in the ADN4600 family for aerospace applications. I need this information to conduct the SEU analysis for the ADN4600 at a high altitude. 

For memory components operated in aircraft at altitude, random particles can cause a bit to change state.  I need to be able to estimate the likelihood that this would happen for any device containing memory or data registers such as are in the ADN4604.

 An estimate of the area of the chip for this device devoted to the memory registers and the total number of bits in the registers would allow us to determine the Single Event Upset Cross-Section for these devices.

 

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  • +1
    •  Analog Employees 
    on Dec 9, 2020 1:01 PM 4 months ago

    Hi,

    ADN4604 fabricated in the EP120 (0.35 μm BiCMOS) process technology, and packaged in a 100-lead TQFP with exposed pad (epad).

    The die size of ADN4605 device is ~ 4165mm x 353mm, it has a point cell containing the point memory and consumes 40um x 50um layout area.

    Total number of registers are 0x00 to 0xFF with 8-bit width.

    I hope this information can help you to check the soft error rate.

    Regards,

    Siva Kumar.

Reply
  • +1
    •  Analog Employees 
    on Dec 9, 2020 1:01 PM 4 months ago

    Hi,

    ADN4604 fabricated in the EP120 (0.35 μm BiCMOS) process technology, and packaged in a 100-lead TQFP with exposed pad (epad).

    The die size of ADN4605 device is ~ 4165mm x 353mm, it has a point cell containing the point memory and consumes 40um x 50um layout area.

    Total number of registers are 0x00 to 0xFF with 8-bit width.

    I hope this information can help you to check the soft error rate.

    Regards,

    Siva Kumar.

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