I'm looking for soft error rates in FIT/Mb caused by single event upsets (SEUs) affecting memory cells used in the ADN4600 family for aerospace applications. I need this information to conduct the SEU analysis for the ADN4600 at a high altitude.
For memory components operated in aircraft at altitude, random particles can cause a bit to change state. I need to be able to estimate the likelihood that this would happen for any device containing memory or data registers such as are in the ADN4604.
An estimate of the area of the chip for this device devoted to the memory registers and the total number of bits in the registers would allow us to determine the Single Event Upset Cross-Section for these devices.