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ADN4612 - Jitter


For ADN4612, what are the factors determining Jitter performance.

What is the best Jitter performance we can get and what are the settings?

We plan to input clock signal with <50fs jitter. What will be the expected output jitter?

thank you.

best regards

  • Hi,

    ADN4612 datasheet describes PE/EQ optimization vs channel-loss:

    • Figure 7, pg13.  Baseline jitter vs. data rate [best possible, minimum channel] – example eye-diagrams are shown on page 17, fig27-fig30.
    • Figure 13, 14, 16, pg14.  Residual jitter vs. reference channel insertion-loss and Rx-side EQ setting.  (Reference channels are given in Fig 14).  Page 18-19 shows example eyes pre- and post- equalization.
    • Figure 19, Fig 22, pg15.  Residual jitter vs. Tx-side PE setting.  Page 20-21 shows example eyes of jitter before and after Tx-pre-emphasis.

     Other factors to observe:

                  Rx signal amplitude.  (The peak-to-peak low-frequency amplitude requirement should be observed.)

                  Tx signal amplitude and compliance levels.  Reference page 33 and Table 26.  Depending on VTTO supply voltage and Pre-emphasis setting, it is possible to put so much current in the output stage that the resulting common-mode shift across the Tx termination resistors causes the output stage to saturate – which would increase jitter.

    ADI recommendations for better jitter performance:

    1. enabling offset calibration circuits to minimize the offsets in the receiver architecture, as a result it will reduce duty cycle distortion (DCD) contribution to residual deterministic jitter. The offset calibration circuit operates on dc-balanced data streams only. The offset calibration circuit is disabled for all receiver inputs by default. Enable the offset calibration circuit by writing a Logic 1 to the appropriate bit location, as follows:
      1. For the Receiver Input 5 to Receiver Input 0 offset calibration enable, write to Register Address 0xA0.
      2. For the Receiver Input 11 to Receiver Input 6 offset calibration enable, write to Register Address 0xA8.
    2. Every input lane offers a programmable receive equalizer for NRZ data of up to 11.3 Gbps. The programmable equalizer settings to provide optimum jitter performance over a broad range of input channel lengths.
    3. The device provides programmable current driver settings and LSB step size for each driver element, that provide a wide range of FIR filter shape to generate a transmit equalization response that closely match the inverse of the channel loss, as a result it minimizes the overall residual jitter in the signal.

    If the question is additive rms jitter, table 1 on page 4 describes random jitter as 500fs typical.  The usual calculation is the noise of a 50fs input clock signal should RSS with the device’s additive jitter.  Since this device was characterized with a signal source with roughly 250fs rms jitter, an input clock signal with 50fs rms jitter should appear with ~500fs rms jitter on the output.

    ADN4612 device is asynchronous and no clock is required. It supports a broad range of frequency operation from dc-11.3 Gbps on any lane with no restriction to data rate on other lanes.  The switch is non-blocking, and any input may be routed to any and multiple outputs.

    It looks like you are using ADN4612 as clock/buffer distribution device, If so, ADI has a line of products designed and optimized just for those applications.


    Siva Kumar.