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Urgent: ADRF5027-EVALZ stops working after few iterations


We’ve been iterating with 2-3 EVALZs for ADRF5027 and all of them stopped working after one or two experiments. We’d like to figure out why this is happening every time. So, here is the details of our operational process and our observations:

The chip requires dual-supply voltage of +3.3V and -3.3V. We’ve been using Keysight E36300 Triple output power supply by setting the corresponding voltages and the maximum current of 0.001A (this is the minimum value the power supply can be set to).

However, after we connected the loads to the eval board, we noticed that the voltages (sometimes the positive and sometimes the negative voltage) fluctuate a lot between the absolute values of 1.5V and 3.3V and sometimes it fixes on lower values (~1.6V). Our speculation was that the current is set too low. So, we increased the current to 0.1A (and sometimes 0.5A), which solved the voltage fluctuation but the chip draws a lot more current that the typical values in the datasheet (the typical values are 2uA for positive and 100uA for negative supply current, while the chip sometimes draws 0.1A to 0.3A). So, my questions are:

  1. Should we limit the supply current based on the datasheet?
  2. Is it OK if the chip draws more current than the typical values?
  3. We followed the power-up sequence based on the data sheet, by enabling the GND, VDD, and VSS sequentially, then powering up the digital control inputs from a Raspberry Pi (with 3.3v power on control pins - we also have a connection between the chip’s GND pin and RPi’s GND). However, we noticed that sometimes the supply powers drop to 1.6V, while the control pins are still set to 3.3v sourcing from RPi. Could that cause any problem and what is the best practice to avoid damaging the chip?
  4. Should the power driving the VDD, VSS and the control pins come from the same source?
  5. We haven’t add any bypassing capacitor on the supply lines assuming that the Keysight power supply is already filtering high frequency noise. Do you think that could be the reason of frying chip?
  6. What is your recommended process for powering the chip?

  • Hi,

    1. You should limit the current based on the datasheet. The reason is that if something is wrong in your setup, e.g. the overshooting current won't damage the part in a short period of time. I just would like to clarify that you do not need to supply current. You should supply voltage only, and limit the current.

    2. I do not think it is OK if the chip draws more current than typical, especially in your case, it is way much higher. 0.1A to 0.3A current very likely indicates that the part was damaged.

    3. The supply voltage should hold at 3.3V and -3.3V. They should not fluctuate no matter if you have control pins biased or unbiased. Can you double check if your Keysight power supply works correctly? 

    4. I would suggest use one source for each pin, but all the grounds should be routed together and connect to the evaluation board ground. 

    5. Bypassing capacitors will filter high frequency noise, but I do not think it will damage the chip without adding them.

    6. The recommended process for powering the chip is to follow the "Theory of Operation" section of the datasheet. You should power up Vdd and Vss before powering up Ven and Vctrl.

    7. I would suggest you ground the Ven and Vctrl pins first, and power up Vdd, then Vss. This will isolate the Raspberry Pi from Keysight supply. This setup will result in insertion loss (on) from RF2 to RFC. Then carefully monitor the current of Vdd and Vss. They should be the typical value on the datasheet, and the voltage should not fluctuate. Otherwise, I am guessing your Keysight supply might not work correctly. You can use an oscilloscope to check the waveform of the supply output.

  • Thanks for your reply. We checked our Keysight power supply and it works fine. Also, we are not supplying current, only voltage, but we can limit the current on the power supply and the problem is that with all of the 3 versions of the eval board that we tried, the drawing current was a lot more than the typical values in the datasheet. On the other hand, setting the current limit too low (e.g 0.001A) does not allow the board to draw enough voltage and it does not work. We have also designed a new power supply board to hold the powering sequence automatically, but could limit the current at 500mA only and we don't have the flexibility of getting the limits as low as 100uA recommended by the datasheet! So, I'm really confused how we can use this chip reliably without it getting damaged so easily!

  • I would like to clarify that 2uA Idd and 100uA Iss is the typical value for VDD and VSS pins. Limiting the current will only help once there is a short circuit and the current is way higher to damage the part, so it will not change how the part should perform. Therefore, I am wondering if there is anything wrong with the power supply circuit. Could you send me the schematic of the power supply board? I would like to take a look and review with the team.

  • Hi,

    We went through multiple iterations of the power supply design. Here is the final version. Can you take a look at the schematic and let me know what you think? Also, can you tell me what is the maximum switching rate (or minimum switching period) that we can expect this switch to fully operate at? the numbers on the datasheet is a little bit confusing. I reduced the switching period to as low as 100us, but the output does not match.


    mmTag RevB.tif

  • Hi,

    I did not see anything unusual in the schematic.

    In the datasheet of ADRF5027, the rise time is 1.3us and the switching time is 3.6us. Therefore, about 2.3us delay comes from the digital path. In your case, 100us should be long enough.


  • Thanks for your reply. How did you come up with 2.3us digital path delay? In the data sheet, there's also two numbers for the "RF Settling Time". How do these values affect the minimum switching period? 

    So, is the following analysis correct?

    1.3us rising time + 1.3us falling time + 3.6 switching time => minimum switching period  6.2us

  • 2.3us digital path delay = 3.6us switching time - 1.3us rise time. The switching period should be longer than 2.3us in order for the switch to react with the coming digital control signal.

  • Hi Zwang, I have the exact same problem with the same chip.

    I am residing in Munich and would appreciate it if you give me instruction how to solve this problem!