I do see that ADG439 supports Fault protection, but i would like to understand the internal structure how the fault protection is implemented. Please provide the internal diagram of implementation.
The theory of operation section on page 13 of the ADG439F datasheet details the internal fault protection structure.
I would like to understand how Enable pin is controlling the operating of IC. I meant i would like to understand the internal structure, it would be helpful if we can get screenshot ,so we can analyze and check how we can utilize it for our application.
The Enable pin is and active High Digital Input. When low, the device is disabled, and all switches are off.
Regarding the internal structure I'm not sure I understand what you are looking for. Is there something we are missing from the theory of operation section on the datasheet?
I meant When Vdd is removed and then we send a low on "Enable" pin, can the switches be turned Off?