ADG1414 datasheet Rev.B refers to "SCLK active edge" but does not define it.
a) In Figure 2, details "t4" and "t9", it seems as if SCLK rising edge would not be an active edge. However, in figure 3 detail t9 is referred to a rising edge and the caption mentions that that end would be an "active edge". What am I missing? Is the rising edge of SCLK an "SCLK active edge" or not?
b) Does the SCLK have to be low when SYNCb goes up?
Thanks for your query on the ADG1414.
For the ADG1414 the data is clocked in on the SCLK falling edge, and it is transferred out on SDO on the rising edge of SCLK. So in fact both edges are considered "Active"
Does the SCLK have to be low when SYNCb goes up?
No but it must be in a steady state for 5 ns after SYNCb is brought up. This is was is shown by t9 in figure 3.
I hope this helps, let me know if you have any more questions