I'm using Transceiver Toolbox with Simulink for HDL targeting on zc706+ad9371 on Windows. I found that my design failed to meet the timing requirements, the slack time of 'clk_fpga_0 to mmcm_clk_0_s_1' in 'inter-clock paths' is negative. In order to check whether the problem comes from my own design, I built a simple pass through model with Simulink:
With Transceiver Toolbox v23.2.1, I used the HDL workflow advisor to compile the project targeting platform zc706. After finishing all steps, vivado successly generated the BOOT.bin file. But when opening the vivado project, I find that the timing violation still exists, even for this pass through simple project. The vivado outputs are shown here:
Eventually, in order to check if this problem exists only in Transceiver Toolbox, I cloned the hdl reference designs from github and compile the zc706+adrv9371x project (direcly using make). This time there is no violation:
It seems that the violation happens with maybe the clock signal of my IP core's AXI lite interface? I tried other implementation strategies, but I got no luck.
So why did this happen and should I solve this problem? If so, How? I've attach my Simulink slx file below, it runs in version r2023b. I understand that it should be easy to reproduce this issue with Transceiver Toolbox.
