I'm using an AD9371 for a custom IP application with DPD. I have built the simulink model and want to use HDL targeting workflow provided by ADI.
I expect to use two ADC input, one of them is the receive path and the other is observation path, so that some DPD algorithm can be done on my IP logic.
However, it seems there's only two ADC input path in the HDL workflow target interface, as shown:
I presume they are for two receive path instead of observation path? Does this mean that for AD9371 and AD9375, it's not possible to design custom FPGA IP for observation input on simulink?