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Issues connecting to FCOMMS3 when using the Transceiver toolbox

Category: Software
Product Number: ZC706 Evaluation Board

Hello there,

I am currently setup is using a ZYNQ 706 evaluation board with an AD-FCOMMS3-EBZ.all connected to my host computer. I am running MATLAB version 2020b, AD Transceiver Toolbox version 22.2.1 and Xilinx 2021.2.

I have been going through the process of converting a Simulink model into Verilog via the HDL coder on MATLAB to run on the FPGA of the board. I've installed the Transceiver toolbox and am using the IP core generation to target the zynq 706 fcomms3 platform and am able to successfully reach the end of the workflow advisor, generate the bitsream and the BOOT.bin file and then program the board.

However once I have my generated interface model of the system and try to run it, I get an error to connect to the radio. I'm able to ping the zynq board and the radio but when I try the command

dev =  sdrdev('AD936x')


It's able to ping the radio but fails when it tries to communicate from the radio through the zynq board back to the host computer.

I can only get the host computer to connect to the radio successfully when the SD card for the ZYNQ board is configured with the Communications toolbox for Xilinx devices add-on. When I write the transceiver toolbox files to the SD card and use the BOOT.bin file generated from the bitstream step I am unable to connect to the board.

Are the files in the ADI Kuiper Linux image meant to be the only files in the SD card? Ive pulled the necessary platform devicetree and kernel image to the root directory along with the generated BOOT.bin nut still am not able to connect.

Any help would be greatly appreciated

Parents Reply
  • Here is my current software interface model setup.

    For the 4 inputs I've set the target interfaces going into the Xilinx Zynq AXI Interface I set them to AD9361 ADC channel data

    For the 2 outputs I've set them to AD9361 DAC channel data.

    the goal is to take in 2 signals from Rx1 and Rx2 of the FCOMMS3 board, have them undergo post-processing from the Xilinx Zynq block in the fpga and re transmit the 1 signal that gets outputted by our post processing. I'm trying to observe these signals being received by the transceiver and being outputted by the fpga to confirm its working as intended.