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PyADI-JIF for VCU118: Cannot validate reference design vcu118_ad9081_m8_l4

Category: Software
Product Number: N/A
Software Version: 1.7.5

Hi,

I'm trying understand and use the PyADI-JIF tool for JESD configuration. I've began by trying to validate the existing, functional vcu118_ad9081_m8_l4 design with the script included below, as a sanity check. However, whenever I run the script I get the Exception: "DAC rate too slow for configuration 737280000.0 (min: 2900000000.0)". I've tried to tweak the variables but can't get it to work. Can you tell me where I'm going wrong and how can use PyADI-JIF to validate JESD configurations for an AD9081<->VCU118 design, please?

The script has been modified from the ad9081_rxtx_example.ipynb example. I used the parameters in the vcu118_ad9081_m8_l4.dts device tree to populate the parameters.

Apologies for including the code as an image, the insert code function wouldn't work when writing this question and provided no feedback as to why.

Kind regards,

Deng

  • Your code does not generate the error "DAC rate too slow". It does give you an error w.r.t. the lane rate, which is expected.  I think you are interpreting sample_clock incorrectly. sample_clock is the sample rate into the JESD framers, so after the decimation stages. In the base example you will see something like:

    sys.converter.dac.sample_clock = int(7.2e9) / (12 * 1)

    sys.converter.dac.interpolation = 12

    So this will make the model have a converter rate of 7.2e9 and a sample rate of 600e6.

    Note that for clock solving decimation and interpolation are the only used properties for relating converter_clock and sample_clock. The {cduc/cddc/fduc/fddc}_{interpolation/decimations} are only used for devicetree generation.

    -Travis

  • Travis,

    Thanks for the reply!

    Apologies, your correct - the error was "DAC rate too slow". I updated the script to the following:



    (it still won't allow me to paste in the code, I'm afraid Disappointed)

    This provided the following output:

    DAC Lane rate: 10000000000.0
    ADC Lane rate: 10000000000.0
    {'clock': {'n2': 3125,
               'out_dividers': [6, 3072, 3072, 48, 12, 48, 12],
               'output_clocks': {'AD9081_ref_clk': {'divider': 6,
                                                    'rate': 500000000.0},
                                 'adc_fpga_link_out_clk': {'divider': 12,
                                                           'rate': 250000000.0},
                                 'adc_fpga_ref_clk': {'divider': 48,
                                                      'rate': 62500000.0},
                                 'adc_sysref': {'divider': 3072, 'rate': 976562.5},
                                 'dac_fpga_link_out_clk': {'divider': 12,
                                                           'rate': 250000000.0},
                                 'dac_fpga_ref_clk': {'divider': 48,
                                                      'rate': 62500000.0},
                                 'dac_sysref': {'divider': 3072, 'rate': 976562.5}},
               'r2': 128,
               'vco': 3000000000.0,
               'vcxo': 122880000.0,
               'vcxo_doubler': 1},
               ...continues...

    Are these values supposed to reflect the following values in the linux/arch/microblaze/boot/dts/vcu118_ad9081_m8_l4.dts?

    ...
    
    &hmc7044 {
    
    	adi,pll2-output-frequency = <3000000000>;
    
    	hmc7044_c0: channel@0 {
    		reg = <0>;
    		adi,extended-name = "CORE_CLK_RX";
    		adi,divider = <12>;	// 387.5
    		adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;	// LVDS
    	};
    	hmc7044_c2: channel@2 {
    		reg = <2>;
    		adi,extended-name = "DEV_REFCLK";
    		adi,divider = <12>;	// 387.5
    		adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;	// LVDS
    	};
    	hmc7044_c3: channel@3 {
    		reg = <3>;
    		adi,extended-name = "DEV_SYSREF";
    		adi,divider = <1536>;	// 12.109375
    		adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;	// LVDS
    	};
    	hmc7044_c6: channel@6 {
    		reg = <6>;
    		adi,extended-name = "CORE_CLK_TX";
    		adi,divider = <12>;	// 122880000
    		adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;	// LVDS
    	};
    	hmc7044_c8: channel@8 {
    		reg = <8>;
    		adi,extended-name = "CORE_CLK_RX_ALT2";
    		adi,divider = <12>;	// 250
    		adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;	// LVDS
    	};
    	hmc7044_c10: channel@10 {
    		reg = <10>;
    		adi,extended-name = "CORE_CLK_RX_ALT";
    		adi,divider = <12>;	// 387.5
    		adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;	// LVDS
    	};
    	hmc7044_c12: channel@12 {
    		reg = <12>;
    		adi,extended-name = "FPGA_REFCLK2";
    		adi,divider = <6>;	// 775
    		adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;	// LVDS
    	};
    	hmc7044_c13: channel@13 {
    		reg = <13>;
    		adi,extended-name = "FPGA_SYSREF";
    		adi,divider = <1536>;	// 12.109375
    		adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;	// LVDS
    	};
    };
    
    ...

    If not, can you tell me where/how I can verify the values it's output?

    As a side note: I believe the commented values (e.g., "// 387.5),  in the linux/arch/microblaze/boot/dts/vcu118_ad9081_m8_l4.dts, may be incorrect because they're not equal to adi,pll2-output-frequency divided by the adi,divider. Reading the associated registers on the device (/sys/bus/iio/devices/iio:device0), the values  don't match what's commented in the .dts. 

    Thanks,

    Deng

  • Yes. They need to be reflected into the divider settings. Please ignore the commented rates, sometimes these get copy and pasted from other boards.

    Not all clocks are used in the design (please see the HDL), and there can be nuances in the design since JIF assumes some specific clocking structures in the HDL that are not always implemented. Besides the clocks you need to update the JESD nodes, including transceivers. adi,sys-clk-select and adi,out-clk-select are particularly important.

    -Travis