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ADRV9001+ZCU102 HDL Coder - Missing data in user IP

Category: Hardware
Product Number: ADRV9002
Software Version: 2019R2


using the Transceiver Toolbox 21.1.1 on MATLAB R2021b I have created an FPGA design with HDL Coder targeting the ADRV9002 - ZCU102 platform.

On the Tx Path, if I sent a fixed sequence of data and monitor the data interface between upack2 and the HDL Coder user IP, some data appears not to be either received by upack2 or retrieved correctly by the user IP. What is interesting is that It is constantly the same data in the same position in the data sequence, those that appear as 0x7fff on the image.

The test sequence is as follows:

- Configure adi.ADRV9002.Tx system object with data source DMA and only channel 1 enabled. No custom profile loaded.
- Configure user IP (aka HDL Coder IP). Transmission from user IP to DAC is disabled.
- Transmit data to upack2 with the adi.ADRV9002.Tx system object step function.
- Enable transmission on the user IP. The user IP starts driving the fifo_rd_en signal on the upack2 FIFO.

The data is captured by ILA triggering on the FIFO data valid output.

Really appreciate some support here.