I am trying to get ZCU102 + AD9081 FMC working at a sample rate of 4 GSPS on DAC, and 2 GSPS on ADC. I don't want to use interpolation or decimation in either main or channel paths.
pyadi-jif tool tells me this setup is valid:
So I am using the following JESD204C setups:
'jesd_adc': {'CS': 0,
'F': 3,
'HD': 0,
'K': 256,
'L': 8,
'M': 4,
'Np': 12,
'S': 4,
'bit_clock': 12375000000.0,
'converter_clock': 2000000000.0,
'jesd_class': 'jesd204c',
'jesd_mode': '27.0',
'multiframe_clock': 1953125.0,
'sample_clock': 2000000000.0},
'jesd_dac': {'CS': 0,
'F': 1,
'HD': 0,
'K': 256,
'L': 8,
'M': 1,
'Np': 16,
'S': 4,
'bit_clock': 8250000000.0,
'converter_clock': 4000000000.0,
'jesd_class': 'jesd204c',
'jesd_mode': '20',
'multiframe_clock': 3906250.0,
'sample_clock': 4000000000.0}}
I build the reference AD9081 HDL project with the make parameters:
make JESD_MODE=64B66B RX_LANE_RATE=12.375 RX_JESD_L=8 RX_JESD_M=4 RX_JESD_S=4 TX_LANE_RATE=16.375 TX_JESD_L=8 TX_JESD_M=1 TX_JESD_S=4
I've verified that the FPGA bitstream is getting into the BOOT.BIN correctly as I have altered some LEDs on the output, so I can see that my bitstream is loaded successfully.
I can change my DTS and compile the device tree DTB, and I can successfully get other JESD setups working. I just seem to be missing something wrong with this configuration.
I will attach my DTS file that should match this configuration as well.
Any help would be greatly appreciated.