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pyadi-jif usage: no solutions found in default example (known good config)

Category: Software
Software Version: pyadi-jif main branch, commit 631d1bc


I am trying to use pyadi-jif to validate JESD settings for my ZCU102 <-> AD9081 FMC eval board. 

Using, some configurations which I think should pass can't find a solution.

Notably, the code (unchanged) from github configures for JESD204C, TX Mode 0, RX Mode 1.0, as below:

sys.fpga.sys_clk_select = "GTH34_SYSCLK_QPLL0"  # Use faster QPLL
sys.Debug_Solver = True
sys.converter.clocking_option = "integrated_pll"
sys.fpga.out_clk_select = "XCVR_REFCLK"  # force reference to be core clock rate
sys.converter.adc.sample_clock = 2900000000 / (8 * 6)
sys.converter.dac.sample_clock = 5800000000 / (4 * 12)

sys.converter.adc.decimation = 8 * 6
sys.converter.dac.interpolation = 4 * 12

mode_tx = "0"
mode_rx = "1.0"

This matches the configuration that is set up in the latest boot configuration:

Booting with this I can see the JESD link is happy.  However, the JIF tool tells me there is no solution. 

Is there some user error here?  Any advice appreciated.



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