pyadi-jif usage: no solutions found in default example (known good config)

Question

Hi, 
 I am trying to use pyadi-jif to validate JESD settings for my ZCU102 <-> AD9081 FMC eval board. 
 Using ad9081_rxtx_hmc7044.py, some configurations which I think should pass can't find a solution. 
 Notably, the code (unchanged) from github configures for JESD204C, TX Mode 0, RX Mode 1.0, as below: 
 
 sys . fpga .setup_by_dev_kit_name( "zcu102" ) 
 sys . fpga .sys_clk_select = "GTH34_SYSCLK_QPLL0" # Use faster QPLL 
 sys . Debug_Solver = True 
 sys . converter . clocking_option = "integrated_pll" 
 sys . fpga .out_clk_select = "XCVR_REFCLK" # force reference to be core clock rate 
 sys . converter .adc.sample_clock = 2900000000 / ( 8 * 6 ) 
 sys . converter .dac.sample_clock = 5800000000 / ( 4 * 12 ) 
 
 sys . converter .adc.decimation = 8 * 6 
 sys . converter .dac.interpolation = 4 * 12 
 
 mode_tx = "0" 
 mode_rx = "1.0" 
 
 This matches the configuration that is set up in the latest boot configuration: /latest_boot_partition/zynqmp-zcu102-rev10-ad9081/204c_txmode0_rxmode1 Booting with this I can see the JESD link is happy. However, the JIF tool tells me there is no solution. 
 Is there some user error here? Any advice appreciated. 
 
 Thanks! 
 Matt

travisfcollins · Accepted Answer

We've updated the out_clk_select constraints a bit to better capture the hardware since that example was written. I've updated the example to use PROG_DIV since XCVR_REFCLK assumed a different internal reference design structure. Commenting out sys_clk_select will now automatically determine the transceiver muxing necessary as well. 
 Can you try the updated version that has been merged into main. 
 -Travis)

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pyadi-jif usage: no solutions found in default example (known good config)

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