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sometime pyadi receives on only first 2 channel instead of all 4 channel on FMCOMMS5

Category: Software
Product Number: FMCOMMS5 with ZC702

Run below code on ZC702 with Aug 3 2022 image:

import time
import adi

sdr = adi.FMComms5("ip:127.0.0.1")

record_duration = 0.25 * 1e-3
rx_lo = 2412000000
rx_gain = 30
rx_rf_bandwidth = 20000000
sample_rate = 20000000

sdr.sample_rate = sample_rate
sdr.rx_rf_bandwidth = rx_rf_bandwidth
sdr.rx_rf_bandwidth_chip_b = rx_rf_bandwidth

sdr.rx_lo = rx_lo
sdr.rx_lo_chip_b = rx_lo

gain_control_mode = "manual"
sdr.gain_control_mode_chan0 = gain_control_mode
sdr.gain_control_mode_chan1 = gain_control_mode
sdr.gain_control_mode_chip_b_chan0 = gain_control_mode
sdr.gain_control_mode_chip_b_chan1 = gain_control_mode

sdr.rx_hardwaregain_chan0 = rx_gain
sdr.rx_hardwaregain_chan1 = rx_gain
sdr.rx_hardwaregain_chip_b_chan0 = rx_gain
sdr.rx_hardwaregain_chip_b_chan1 = rx_gain

sdr.rx_enabled_channels = [0, 1, 2, 3]

# this is buffer size in samples for one channel
rx_buffer_size = int(record_duration * sample_rate)
sdr.rx_buffer_size = rx_buffer_size

time.sleep(1) # reserve for FPGA to response

data = sdr.rx()

for idx in range(10):
print("%5d+%5dj %5d+%5dj %5d+%5dj %5d+%5dj" % (
np.real(data[0][idx]), np.imag(data[0][idx]),
np.real(data[1][idx]), np.imag(data[1][idx]),
np.real(data[2][idx]), np.imag(data[2][idx]),
np.real(data[3][idx]), np.imag(data[3][idx])))

sdr.rx_destroy_buffer()
Four running result are shown as below:
analog@analog:~/workspace/fmcomms5_py $ python3 fmcomms5_py_source.py
-2+ 1j 1+ 0j -3+ -10j -1041+-1041j
-1+ 0j -3+ -1j -3+ -10j -1041+-1041j
0+ 2j -2+ 0j -3+ -10j -1041+-1041j
0+ -1j 1+ 0j -3+ -10j -1041+-1041j
0+ 0j 1+ 2j -3+ -10j -1041+-1041j
-1+ 0j -1+ 1j -3+ -10j -1041+-1041j
0+ -2j -1+ 1j -3+ -10j -1041+-1041j
0+ 1j 1+ 0j -3+ -10j -1041+-1041j
-1+ 0j 3+ 0j -3+ -10j -1041+-1041j
1+ 0j -2+ -1j -3+ -10j -1041+-1041j
analog@analog:~/workspace/fmcomms5_py $ python3 fmcomms5_py_source.py
-1+ 0j -1+ -2j 1+ 0j 0+ 1j
1+ 0j -1+ -2j 1+ 0j 1+ 2j
0+ 1j 0+ 1j -1+ 0j -1+ 1j
0+ 1j -1+ 0j 1+ -1j -2+ 0j
-1+ 1j 1+ 0j 0+ 1j 0+ 0j
0+ -1j 2+ -1j -1+ -1j -1+ 0j
0+ 0j 1+ 0j -1+ -1j 1+ 0j
1+ 0j 1+ 0j -1+ 0j 0+ 0j
-1+ -2j 1+ 1j 0+ 0j -3+ 1j
0+ -1j -2+ 0j -1+ 1j 0+ 1j
It is easy to see that ch0/1 are correct for two running. But ch2/3 are not correct for the first running. When ch2/3 are correct are totally randomly, sometimes it can repeat the error for tens time.
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  • I recreated the image from beginning in case of any error. When doing adi_update_tools.sh, I noticed:

    *** Updating libad9361-iio BRANCH origin/2021_R1 ***
    HEAD is now at fd44358 Fix flags for FMComms5 python tests
    ......
    From github.com/.../libad9361-iio
    * [new branch] staging/ci-update -> origin/staging/ci-update

    *** Building libad9361-iio ***

    So after all update done, I clone libad93610-iio and went to staging/ci-update, and follow your instruction. And then run that python code but still a lot error.

    Then I reinstall with sudo pip install ., it still has the problem and the error probability is  about 30%, lower than before. if running the python code with sudo privilege, seems no much difference.

    I can still tolerate it if just in this error rate. But after developing a new code with loop to repeat receiving many times, New problem comes. The code is as below. It includes a small code to check if data are received correctly or not

    from scipy import io
    import numpy as np
    import time
    import adi

    sdr = adi.FMComms5("ip:127.0.0.1")

    record_duration = 10 * 1e-3
    rx_lo = 2412000000
    rx_gain = 10
    rx_rf_bandwidth = 20000000
    sample_rate = 20000000

    sdr.sample_rate = sample_rate
    sdr.rx_rf_bandwidth = rx_rf_bandwidth
    sdr.rx_rf_bandwidth_chip_b = rx_rf_bandwidth

    sdr.rx_lo = rx_lo
    sdr.rx_lo_chip_b = rx_lo

    gain_control_mode = "manual"
    sdr.gain_control_mode_chan0 = gain_control_mode
    sdr.gain_control_mode_chan1 = gain_control_mode
    sdr.gain_control_mode_chip_b_chan0 = gain_control_mode
    sdr.gain_control_mode_chip_b_chan1 = gain_control_mode

    sdr.rx_hardwaregain_chan0 = rx_gain
    sdr.rx_hardwaregain_chan1 = rx_gain
    sdr.rx_hardwaregain_chip_b_chan0 = rx_gain
    sdr.rx_hardwaregain_chip_b_chan1 = rx_gain

    sdr.rx_enabled_channels = [0, 1, 2, 3]

    # this is buffer size in samples for one channel
    rx_buffer_size = int(record_duration * sample_rate)
    sdr.rx_buffer_size = rx_buffer_size

    time.sleep(1) # reserve for FPGA to response

    err_cnt = 0
    for cnt in range(100):
        time.sleep(0.01)
        data = sdr.rx()
        if ((data[2][0] == data[2][1]) and (data[3][0] == data[3][1])): # check if data is correct
            err_cnt = err_cnt + 1
            sdr.rx_destroy_buffer()
            sdr.rx_buffer_size = rx_buffer_size

    print(err_cnt)
    Below is output to use a shell script to call above code for many times:
    [sudo] password for analog:
    Thu 08 Sep 2022 10:52:29 PM PDT
    0
    Thu 08 Sep 2022 10:53:03 PM PDT
    100
    Thu 08 Sep 2022 10:53:43 PM PDT
    0
    Thu 08 Sep 2022 10:54:17 PM PDT
    100
    Thu 08 Sep 2022 10:54:57 PM PDT
    0
    Thu 08 Sep 2022 10:55:31 PM PDT
    100
    Thu 08 Sep 2022 10:56:11 PM PDT
    0
    Thu 08 Sep 2022 10:56:45 PM PDT
    100
    It shows a big problem: once the code did not get right result for the first time in a loop, then it repeats to get wrong result till loop ends. This cannot be tolerated in my app.
    In fact, what I want to do is to get FMComms5's four RX channel sample in a time synchronized way (phase sync is not necessary). Any code (C, grc or python) that can achieve this function are OK. But the first step was blocked here for weeks.
  • It works. Most of time the loop run successfully for 100 times. Sometimes it fails just 1 time in 100 iteration. Not perfect, but good enough to start my trial.Thank you a lot, Travis.

  • BTW, the code should run on ZC702 instead of host. Else the problem is still serious.