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ADRV9361: Enabling FPGA IP Transmitter (no software buffer to tx) on power-up?

Category: Software
Product Number: adrv9364-z7020
Software Version: 2022-07-08-ADI-Kuiper-full.img: 48c3fc7e4de042624d4e7c426179f549

I have built an IP core in the ADRV9361-Z7020 that transmits a custom waveform. However, on power-up the board will always choose DDS first. Using Python, i wrote a script to command the ADRV9361 to switch from DDS to DMA. The IP core I have written replaces DMA data with its own generated IQ samples so switching to DMA is the work-around I've found to get the design to transmit my FPGA generated waveform.

# Create a device interface
sdr = adi.ad9361()
# Configure properties
sdr.rx_rf_bandwidth = 6000000
sdr.tx_rf_bandwidth = 6000000
sdr.rx_lo = 2000000000
sdr.tx_lo = 2000000000
sdr.sample_rate = 800000
sdr.tx_hardwaregain_chan0 = 0
sdr.gain_control_mode_chan0 = "slow_attack"
sdr.dds_enabled = [True, True, False, False]

sdr.tx_enabled_channels = [False, False]

Tx_buf = np.array([[1, 2, 3, 4], [5, 6, 7, 8]])
sdr.tx(Tx_buf)

input("Press any key to stop transmitting...")

Using IIO Oscilloscope with Tx/Rx looped-back I was able to see the custom Tx waveform.

A few questions:

1) Is the correct way of commanding the device to transmit from an FPGA-IP versus DDS? Or is there a better / more documented way? I found this out through trial/error

2) As soon as the Python script ends the ADRV9361 will revert back to DDS - most likely because the object is cleared. Is there a way to prevent this? I'd like the transmitter to continue to use the I/Q samples supplied by the FPGA IP block and not use DDS.

3) A better solution may be to modify the Vivado project to always transmit from the FPGA-IP block on power-up without software intervention. Does such a solution exist? (ie: wire a constant TRUE to some of the enable lines for the axi_ad9361 IP block? Or is that not sufficient and further register poking is required)

Thanks 



edited questions
[edited by: dglee_bc at 7:31 PM (GMT -4) on 14 Jul 2022]