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How to set sample rate in AD9081 via pyadi-iio

Category: Software
Product Number: AD9081-FMCA-EBZ

Hello,

With pyadi-iio I am able to configure my MxFE AD9081 board connected to Xilinx ZCU102.

However I am not able to change the sample rate on either ADCs or DACs.  On the ZCU102 Linux system, using the paths found here: 
https://wiki.analog.com/resources/tools-software/linux-drivers/iio-mxfe/ad9081#tx_sample_rate

I get for example:

root@analog:~# cat /sys/bus/iio/devices/iio:device2/out_voltage_sampling_frequency
250000000

Can I use the python bindings to set the part up to use a higher sampling rate?  Or does it require some change in the device tree?  I understand this may require some change to the JESD204 settings to support the higher rate.

Any example on using the AD9081 at or least nearer to the max sample rates (12 GSPS for DAC, 4 GSPS for ADC) would be much appreciated.

Best regards,

Matt

  • I found this discussion which answers a lot of my question:

     https://ez.analog.com/linux-software-drivers/f/q-a/548054/ad9081-tx-and-rx-sample-rate 

    In  's response, where I'm not clear now is how to build the device tree for my particular board set (zcu102 and AD9081-FMCA-EBZ) - none of the options on the linked page match this configuration.

    Thanks!

    Matt

  • Changing the sample rate is not a simple operation with JESD-based devices. As it requires changing the clocking configuration between the converter, clock chip, and FPGA. It can even require re-synthesizing the FPGA design.

    If you can stick to the current JESD mode, basically ignore the HDL aspect for now, you will need to do two things.

    1. Validate a know good configuration for the clock chip, converter, and FPGA clocks. There is a tool that can help called pyadi-jif which does this validation. Example: https://github.com/analogdevicesinc/pyadi-jif/blob/main/examples/ad9081_rxtx_hmc7044.py Doc: https://analogdevicesinc.github.io/pyadi-jif/master/ .  pyadi-jif proves out the clocks for the different components and will solve for good configurations.

    2. Once you know the config will work for that rate you will need to translate it to devicetree. Here is documentation on configuring devicetree for AD9081: https://wiki.analog.com/resources/tools-software/linux-drivers/iio-mxfe/ad9081#device_tree_customization 

    For advanced users and likely contains bugs: There is some early beta work that will generate the devicetree fragment for you from the pyadi-jif generated structs which is part of the devicetree manager we maintain with pyadi-dt. Example: https://github.com/analogdevicesinc/pyadi-dt/blob/main/examples/ad9081_fmc_dts_gen.py  Doc: https://analogdevicesinc.github.io/pyadi-dt/main/

    To use this you would create a config structure from pyadi-jif then feed that to pyadi-dt to generate the dts fragment. Then compile that with the kernel.

    -Travis

  • Hi Travis,

    Thanks for this detailed response.  Sorry for the late reply, I must have missed the notification email!  I'm back looking at this again after some time away from it, and these links are very helpful.

    I think I'm getting close to getting a working setup, but I'm still unclear about a couple things.

    1)   For the AD9081 ADC side, there is a JESD quick configuration mode referred to like:
    adi,link-mode = <10>;            /* JESD Quick Configuration Mode */

    However, my JESD quick configurations for ADC side are in the form "X.Y", for instance "10.1".  How do I translate this into a uint32 value expected by the adi,link-mode ?


    2) What JESD changes will require an HDL change?  I see that the HDL project is set up for 8 Lane width in the parameters, so I would think I can do up to 8 lanes.  I don't see other JESD parameters in the HDL so I'm assuming they can be programmed, but maybe I'm missing something.

    Thanks again!
    Matt

  • 1. This is just the JTX_MODE from the table

    2. The HDL should be built based on the JESD params of the desired mode. These are set by command line arguments to make or by modifying the top level system_project.tcl file.

    -Travis

  • I think I found the table you are referring to in the adijif/converters/resources folder.  If I'm reading this correctly, bits [7:6] are for the ".Y" and bits [5:0] are for the "X". 
    So to do 10.1 I'd need to write binary 01 001010, or 0x4A:

    adi,link-mode = <0x4A>;

    Is that correct?

    On the HDL question, thanks, I see all the parameters now.  It seems like I will need to rebuild the project with these parameters changed for this to work.

  • JTX_MODE I was referring to was from the UG but the one in pyadi-jif are the same.

    -Travis

  • Hi Travis,
    Following up on the HDL changes for JESD lane rate changes:

    I ran the ad9081_fmca_ebz/zcu102 make, passing in the parameters like this
    make JESD_MODE=64B66B RX_LANE_RATE=12.375 RX_JESD_L=8 RX_JESD_M=4 RX_JESD_S=4 TX_LANE_RATE=16.375 TX_JESD_L=8 TX_JESD_M=1 TX_JESD_S=4

    Build completed successfully.  I was scanning the log after the build, and I noticed the following warnings:
    WARNING: [Synth 8-3301] Unused top level parameter/generic RX_LANE_RATE
    WARNING: [Synth 8-3301] Unused top level parameter/generic TX_LANE_RATE
    WARNING: [Synth 8-3301] Unused top level parameter/generic RX_JESD_M
    WARNING: [Synth 8-3301] Unused top level parameter/generic RX_JESD_S
    WARNING: [Synth 8-3301] Unused top level parameter/generic RX_JESD_NP
    WARNING: [Synth 8-3301] Unused top level parameter/generic RX_TPL_WIDTH
    WARNING: [Synth 8-3301] Unused top level parameter/generic TX_JESD_M
    WARNING: [Synth 8-3301] Unused top level parameter/generic TX_JESD_S
    WARNING: [Synth 8-3301] Unused top level parameter/generic TX_JESD_NP
    WARNING: [Synth 8-3301] Unused top level parameter/generic TX_TPL_WIDTH
    WARNING: [Synth 8-3301] Unused top level parameter/generic TDD_SUPPORT

    It looks as if most of the parameters are not actually being used in the RTL.

    Is this expected?

    Thank you!
    Matt