Stream data into/out of MATLAB

Hi ,


I want to Stream data into/out of MATLAB

With your tools so I started with the following link:


I then performed the following steps:

I use windows.

And I installed the


Xilinx Vivado 2018.2



I installed Libiio Installers


Now I'm trying to figure out what I should have in SD CARD if at all?



I am using ZC706 + AD9361


Thanks for your help

  • 0
    •  Analog Employees 
    on Apr 1, 2021 1:46 PM

    Please look at the instructions on this page - The image you are looking for needs to be copied to the base directory from the subdirectory as explained in "Preparing the image" section. Let us know if you have questions.

    - Srikanth

  • Hi Srikanth,

    i followed the instructions in the link, write the file to MY SD card.
    Additionally copied the image  to the base directory from the subdirectory

    And I managed to run the example at the following link:


    I am currently interested in an example of targeting from your site.
    What example can you recommend me to use if I use the VIVADO 2019.1 version and the ADI versions I mentioned above?
    And according to what documentation to focus on in order to get guidance ??

    please advise



  • Hi Travis ,

    Do you have any suggestions for a solution?

    Maybe something to do with incompatible versions?
    Maybe you want me to try another example?

  • 0
    •  Analog Employees 
    on Apr 9, 2021 4:51 PM in reply to ron1

    Can you export the HDL Workflow Advisor configuration as a script and post it here?


  • yes

    % HDL Workflow Script
    % Generated with MATLAB 9.8 (R2020a) at 13:16:17 on 10/04/2021
    % This script was generated using the following parameter values:
    % Filename : 'C:\tr_toolbox\hdlworkflow.m'
    % Overwrite : true
    % Comments : true
    % Headers : true
    % DUT : 'ModeS_ADI_Codegen/Detector'
    % To view changes after modifying the workflow, run the following command:
    % >> hWC.export('DUT','ModeS_ADI_Codegen/Detector');

    %% Load the Model

    %% Restore the Model to default HDL parameters

    %% Model HDL Parameters
    %% Set Model 'ModeS_ADI_Codegen' HDL parameters
    hdlset_param('ModeS_ADI_Codegen', 'Backannotation', 'on');
    hdlset_param('ModeS_ADI_Codegen', 'CodeGenerationOutput', 'GenerateHDLCodeAndDisplayGeneratedModel');
    hdlset_param('ModeS_ADI_Codegen', 'HDLSubsystem', 'ModeS_ADI_Codegen/Detector');
    hdlset_param('ModeS_ADI_Codegen', 'OptimizationReport', 'on');
    hdlset_param('ModeS_ADI_Codegen', 'ReferenceDesign', 'FMCOMMS2/3 ZC706 (RX)');
    hdlset_param('ModeS_ADI_Codegen', 'ResourceReport', 'on');
    hdlset_param('ModeS_ADI_Codegen', 'SynthesisTool', 'Xilinx Vivado');
    hdlset_param('ModeS_ADI_Codegen', 'SynthesisToolChipFamily', 'Zynq');
    hdlset_param('ModeS_ADI_Codegen', 'SynthesisToolDeviceName', 'xc7z045');
    hdlset_param('ModeS_ADI_Codegen', 'SynthesisToolPackageName', 'ffg900');
    hdlset_param('ModeS_ADI_Codegen', 'SynthesisToolSpeedValue', '-2');
    hdlset_param('ModeS_ADI_Codegen', 'TargetDirectory', 'C:\tr_toolbox\hdl_prj\hdlsrc');
    hdlset_param('ModeS_ADI_Codegen', 'TargetLanguage', 'Verilog');
    hdlset_param('ModeS_ADI_Codegen', 'TargetPlatform', 'AnalogDevices FMCOMMS2/3 ZC706');
    hdlset_param('ModeS_ADI_Codegen', 'Traceability', 'on');
    hdlset_param('ModeS_ADI_Codegen', 'Workflow', 'IP Core Generation');

    % Set SubSystem HDL parameters
    hdlset_param('ModeS_ADI_Codegen/Detector', 'AXI4SlaveIDWidth', '12');
    hdlset_param('ModeS_ADI_Codegen/Detector', 'ProcessorFPGASynchronization', 'Free running');

    % Set Inport HDL parameters
    hdlset_param('ModeS_ADI_Codegen/Detector/I_In', 'IOInterface', 'AD9361 ADC Data I0 [0:15]');
    hdlset_param('ModeS_ADI_Codegen/Detector/I_In', 'IOInterfaceMapping', '[0:15]');

    % Set Inport HDL parameters
    hdlset_param('ModeS_ADI_Codegen/Detector/Q_In', 'IOInterface', 'AD9361 ADC Data Q0 [0:15]');
    hdlset_param('ModeS_ADI_Codegen/Detector/Q_In', 'IOInterfaceMapping', '[0:15]');

    % Set S-Function HDL parameters
    hdlset_param('ModeS_ADI_Codegen/Detector/CalcNF/NoiseFloor', 'AddPipelineRegisters', 'on');
    hdlset_param('ModeS_ADI_Codegen/Detector/CalcNF/NoiseFloor', 'MultiplierOutputPipeline', 1);

    % Set S-Function HDL parameters
    hdlset_param('ModeS_ADI_Codegen/Detector/CalcSyncCorr/SyncCorr', 'AddPipelineRegisters', 'on');
    hdlset_param('ModeS_ADI_Codegen/Detector/CalcSyncCorr/SyncCorr', 'MultiplierOutputPipeline', 1);

    % Set Outport HDL parameters
    hdlset_param('ModeS_ADI_Codegen/Detector/reset', 'IOInterface', 'AXI4');
    hdlset_param('ModeS_ADI_Codegen/Detector/reset', 'IOInterfaceMapping', 'x"100"');

    % Set Outport HDL parameters
    hdlset_param('ModeS_ADI_Codegen/Detector/bit_process', 'IOInterface', 'AXI4');
    hdlset_param('ModeS_ADI_Codegen/Detector/bit_process', 'IOInterfaceMapping', 'x"104"');

    % Set Outport HDL parameters
    hdlset_param('ModeS_ADI_Codegen/Detector/empty_reg', 'IOInterface', 'AXI4');
    hdlset_param('ModeS_ADI_Codegen/Detector/empty_reg', 'IOInterfaceMapping', 'x"108"');

    % Set Outport HDL parameters
    hdlset_param('ModeS_ADI_Codegen/Detector/bit_clk', 'IOInterface', 'IP Data Valid OUT');
    hdlset_param('ModeS_ADI_Codegen/Detector/bit_clk', 'IOInterfaceMapping', '[0]');

    % Set Outport HDL parameters
    hdlset_param('ModeS_ADI_Codegen/Detector/bits', 'IOInterface', 'AXI4');
    hdlset_param('ModeS_ADI_Codegen/Detector/bits', 'IOInterfaceMapping', 'x"10C"');

    % Set Outport HDL parameters
    hdlset_param('ModeS_ADI_Codegen/Detector/crc', 'IOInterface', 'AXI4');
    hdlset_param('ModeS_ADI_Codegen/Detector/crc', 'IOInterfaceMapping', 'x"110"');

    % Set Outport HDL parameters
    hdlset_param('ModeS_ADI_Codegen/Detector/noise_floor', 'IOInterface', 'AXI4');
    hdlset_param('ModeS_ADI_Codegen/Detector/noise_floor', 'IOInterfaceMapping', 'x"114"');

    % Set Outport HDL parameters
    hdlset_param('ModeS_ADI_Codegen/Detector/sync_corr', 'IOInterface', 'AXI4');
    hdlset_param('ModeS_ADI_Codegen/Detector/sync_corr', 'IOInterfaceMapping', 'x"118"');

    % Set Outport HDL parameters
    hdlset_param('ModeS_ADI_Codegen/Detector/data', 'IOInterface', 'IP Data 0 OUT [0:15]');
    hdlset_param('ModeS_ADI_Codegen/Detector/data', 'IOInterfaceMapping', '[0:15]');

    % Set Outport HDL parameters
    hdlset_param('ModeS_ADI_Codegen/Detector/frame_valid', 'IOInterface', 'IP Data 1 OUT [0:15]');
    hdlset_param('ModeS_ADI_Codegen/Detector/frame_valid', 'IOInterfaceMapping', '[0:15]');

    %% Workflow Configuration Settings
    % Construct the Workflow Configuration Object with default settings
    hWC = hdlcoder.WorkflowConfig('SynthesisTool','Xilinx Vivado','TargetWorkflow','IP Core Generation');

    % Specify the top level project directory
    hWC.ProjectFolder = 'C:\tr_toolbox\hdl_prj';
    hWC.ReferenceDesignToolVersion = '2018.2';
    hWC.IgnoreToolVersionMismatch = false;

    % Set Workflow tasks to run
    hWC.RunTaskGenerateRTLCodeAndIPCore = true;
    hWC.RunTaskCreateProject = true;
    hWC.RunTaskGenerateSoftwareInterfaceModel = true;
    hWC.RunTaskBuildFPGABitstream = true;
    hWC.RunTaskProgramTargetDevice = false;

    % Set properties related to 'RunTaskGenerateRTLCodeAndIPCore' Task
    hWC.IPCoreRepository = '';
    hWC.GenerateIPCoreReport = true;

    % Set properties related to 'RunTaskCreateProject' Task
    hWC.Objective = hdlcoder.Objective.None;
    hWC.AdditionalProjectCreationTclFiles = '';
    hWC.EnableIPCaching = false;

    % Set properties related to 'RunTaskGenerateSoftwareInterfaceModel' Task
    hWC.OperatingSystem = 'Linux';

    % Set properties related to 'RunTaskBuildFPGABitstream' Task
    hWC.RunExternalBuild = true;
    hWC.TclFileForSynthesisBuild = hdlcoder.BuildOption.Custom;
    hWC.CustomBuildTclFile = 'C:\tr_toolbox\hdl_prj\vivado_ip_prj\projects\scripts\adi_build.tcl';

    % Set properties related to 'RunTaskProgramTargetDevice' Task
    hWC.ProgrammingMethod = hdlcoder.ProgrammingMethod.Download;

    % Validate the Workflow Configuration Object

    %% Run the workflow
    hdlcoder.runWorkflow('ModeS_ADI_Codegen/Detector', hWC);

  • Hi Travis,

    Can I perhaps pass on more information that can help solve my problem?

    Maybe try running on a different example or version?



  • 0
    •  Analog Employees 
    on Apr 13, 2021 9:34 PM in reply to ron1

    This booted fine for me with the 2019-R2 kernel. My guess would be you might have a corrupted FSBL. I would recommend using at least 20.1.2 as 20.1.1 is out of our support window.

    An alternative is using the Demo from MathWorks:


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