Hello to everyone!
I'm using HW/SW Co-design QPSK Transceiver model in Simulink (zedboard+fmcomms3). In first step my development I use one board and Transmitter Interrupt schedule for loop trigger in model. In System Timing guidelines this schedule describing that: "The loop trigger is an interrupt that occurs when a frame is available for writing to the user logic on the FPGA". It's good solution if use one board. However, I want transmit data from one board to other. For this purpose, I split up model and use TX-part on one board and RX-part on other board. I'm successfully generate code for interface model with Embedded Coder. Model with TX-part work fine. In RX-part model I set Receiver Interrupt schedule (The loop trigger is an interrupt that occurs when a frame becomes available for reading from the receive user logic on the FPGA). But this model not working correctly. Nothing happens after initialization hardware and model is not responding.
Maybe someone faced with similar problem?
I will be grateful for any help you can give me.
You will need to contact MathWorks support for the details around their ARM interrupts. It's outside the scope of our support.
It's likely that you are not able to decode anything upstream. Have you verified that the receiver is able to capture packets in this config before passing them to the ARM?
Receiver good work in TX-interrupt mode. HDL-design and interface model do not have changes in both interrupt mode. How should a RX-interrupt work? What's signal come from hardware to the ARM?