Simultaneous (Full-duplex) Transmission and Reception Using AD9371

We are trying for simultaneous transmission and reception using two AD9371 Transceiver where each set consists of a Xilinx ZCU106 FPGA + AD9371 SDR Transceiver.

We are controlling the Tx and Rx using a Python script. Currently, registers are shared between TX and RX.

The register settings are as follows:

tx_dev.reg_write(0x800000BC, 0x60000121)

tx_dev.reg_write(0xBC, 0x84000000)

Note that half-duplex communications between Tx1 and Rx1, are working fine

For full-duplex, once we execute the Tx2, then Rx1 loses the lock.

Any suggestions? Any Full-duplex reference design using Python and IIO? Where can we find the register map for AD9371? 

 

Top Replies

    •  Analog Employees 
    Apr 20, 2020 in reply to Anowar +1 verified
    These register is used to configure the system parameters such as code rate, sample rate etc. for DVB-S system.

    So these are not related to the transceiver at all then? Are these calls just…

  • 0
    •  Analog Employees 
    on Apr 11, 2020 7:25 PM 3 months ago

    There is no register map available for AD9371, but this should not hinder what you are trying to do.

    We are controlling the Tx and Rx using a Python script. Currently, registers are shared between TX and RX.

    Why do you say this?

    For full-duplex, once we execute the Tx2, then Rx1 loses the lock.

    Can you provide more detail?

    -Travis

  • We are controlling the Tx and Rx using a Python script. Currently, registers are shared between TX and RX.

    Why do you say this?

    I mean the following registers: tx_dev.reg_write(0x800000BC, 0x60000121) and tx_dev.reg_write(0xBC, 0x84000000) are used in the Python scripts that we are considering for Tx and Rx.

    For full-duplex, once we execute the Tx2, then Rx1 loses the lock.

    Can you provide more detail?

    We are using a Python script for frequency sweeping in Rx carrier frequency to obtain the lock between Tx1 and Rx1. Once Rx is locked, we start receiving the signal. However, when we run the transmission using Tx2, then Rx1 loses the lock with Tx1.

  • 0
    •  Analog Employees 
    on Apr 13, 2020 3:48 PM 3 months ago in reply to Anowar
    I mean the following registers: tx_dev.reg_write(0x800000BC, 0x60000121) and tx_dev.reg_write(0xBC, 0x84000000) are used in the Python scripts that we are considering for Tx and Rx.

    What do these do in your code?

    We are using a Python script for frequency sweeping in Rx carrier frequency to obtain the lock between Tx1 and Rx1. Once Rx is locked, we start receiving the signal. However, when we run the transmission using Tx2, then Rx1 loses the lock with Tx1.

    Are you using a non-standard reference design or Linux image? What SD card version are you using?

    -Travis

  • What do these do in your code?

    These register is used to configure the system parameters such as code rate, sample rate etc. for DVB-S system.

    Are you using a non-standard reference design or Linux image? What SD card version are you using?

    We are using standard linux image: 2019_R1-2020_02_04.img.

    The figure below shows the explanation of the problem, we are facing:

  • +1
    •  Analog Employees 
    on Apr 20, 2020 4:46 PM 2 months ago in reply to Anowar
    These register is used to configure the system parameters such as code rate, sample rate etc. for DVB-S system.

    So these are not related to the transceiver at all then? Are these calls just to your IPs registers?

    We are using standard linux image: 2019_R1-2020_02_04.img.

    The figure below shows the explanation of the problem, we are facing:

    We do not support ZCU106 (Maybe you meant ZCU102). Maybe you are basing your code of our ZCU102 design.

    Anyway, what do you want to control from python that you cannot control today?

    -Travis