[ADXL373] What is the register setting for impact mode detection.

We are trying to port impact mode detection on Linux ADXL373 sample driver, but after enabling AWAKE_INT1 bit in INT1_MAP, the INT1 goes to high. I try to read status to clear AWAKE but it still keep high.


Our test condition:

0. Config ADXL373 to impact detection and record peak data into FIFO and let host cpu enter suspend
1. Drop device to ground
2. ADXL372 detect high g force and then generate interrupt to wake up host cpu
3. Host CPU read peak data from FIFO


Our current settings

0x39 FIFO_SAMPLES: 0xAA
0x3A FIFO_CTL: 0x3A
0x3B INT1_MAP: 0x70
0x3C INT2_MAP: 0x70
0x3D TIMING: 0x0
0x3E MEASURE: 0x20
0x3F POWER_CTL: 0x1F

After set INT1_MAP as 0x70, INT1 goes to high and STATUS value is 0x41. It cannot clear the AWAKE interrupt.

  • 0
    •  Analog Employees 
    on Sep 9, 2019 7:44 AM over 1 year ago

    Hello,

    The Awake bit is an indicator that tells you if the part is in movement or stationary, it needs to be linked with activity setting (which isn't set in the above example). Please note that it also behaves differently in different activity modes. Based on the datasheet, the awake interrupt automatically goes high upon entering measurement mode if the device is in default mode or autosleep mode. If it is in linked or loop mode (but not autosleep), it is linked to the activity interrupt (based on the activity threshold the user sets). Please check page 17 and 18 of the datasheet for more details.

    Based on the above settings, you want to use high g force to trigger interrupt to wake up the host uC to read peak value from FIFO. You can directly follow the configuration on page 19 of the datasheet (Capturing impact events) . Please try to set activity & inactivity threshold (from 0x23 to 0x29, 0x29 to 0x31) and use the activity/awake interrupt to trigger the uC.

    Regards,

    -Stefan

  • Hi Stefan, 

    I try to config to linked or loop mode, but the INT1 is always high after enable the INT1_MAP. 

    I try try to implement the impact detection on ADXL373 device based on ADXL372 linux driver. After impact, ADXL373 generate the interrupt and then host read the the FIFO entry register and the data is zero. Please help review register settings and my sample driver. 

     

    LOG:

    [ 9.609432] adxl372_spi_probe+
    [ 9.609701] adxl372_spi_probe -
    [ 9.609716] adxl372_spi spi1.0: adxl372_probe irq 258
    [ 9.611444] adxl372_set_op_mode op_mode 0
    [ 9.611759] adxl372_set_activity_threshold act: 0, ref_e:0 , enable:1, threshold: 5000
    [ 9.612093] adxl372_set_activity_threshold act: 2, ref_e:0 , enable:1, threshold: 100
    [ 9.612428] adxl372_set_act_proc_mode mode 2
    [ 9.612991] adxl372_set_odr odr 4
    [ 9.613556] adxl372_set_bandwidth bw 4
    [ 9.614117] adxl372_set_activity_time_ms act_time_ms 4
    [ 9.614129] adxl372_set_activity_time_ms reg_val 0x1
    [ 9.614333] adxl372_set_inactivity_time_ms inact_time_ms 10000
    [ 9.614345] adxl372_set_inactivity_time_ms reg_val_h 0x3, reg_val_l 0x1
    [ 9.614796] adxl372_set_filter_mode lpf_en 1, hpf_en 1
    [ 9.615899] adxl372_set_filter_settle filter_settle 1
    [ 9.616458] adxl372_set_op_mode op_mode 3
    [ 9.618941] adxl372_spi spi1.0: adxl372_probe ret 0 done
    [ 26.373505] adxl372_set_watermark val: 60
    [ 28.458547] adxl372_set_watermark val: 60
    [ 92.569090] adxl372_write_raw info: 12
    [ 92.569122] adxl372_set_odr odr 2
    [ 92.579323] adxl372_set_activity_time_ms act_time_ms 4
    [ 92.579453] adxl372_set_activity_time_ms reg_val 0x1
    [ 92.588114] adxl372_set_inactivity_time_ms inact_time_ms 10000
    [ 92.588143] adxl372_set_inactivity_time_ms reg_val_h 0x1, reg_val_l 0x81
    [ 92.588948] adxl372_set_bandwidth bw 2
    [ 92.606249] adxl372_buffer_postenable fifo_format:7, fifo_set_size: 3
    [ 92.606268] adxl372_set_op_mode op_mode 0
    [ 92.606890] adxl372_configure_fifo fifo_samples 0x3c
    [ 92.612597] adxl372_configure_fifo fifo_ctl 0x3e
    [ 92.612946] adxl372_set_op_mode op_mode 3
    [ 92.720897] adxl372_set_op_mode op_mode 2
    [ 92.728574] adxl372_set_interrupts int1_bitmask 0x36, int2_bitmask: 0x0
    [ 104.157001] adxl372_accel_irq_handler
    [ 104.160809] adxl372_trigger_handler status1: 0x01, status2: 0x00, fifo_entries: 0  ==> fifo entry is zero

     

    Regards,

    Terry Cheng

  • Hi Stefan, 

    I also test it on full bandwidth measure mode, but fifo entry is still zero after impact interrupt. 

    [ 9.626820] adxl372_spi_probe+
    [ 9.627118] adxl372_spi_probe -
    [ 9.627134] adxl372_spi spi1.0: adxl372_probe irq 258
    [ 9.628458] adxl372_set_op_mode op_mode 0
    [ 9.628770] adxl372_set_activity_threshold act: 0, ref_e:0 , enable:1, threshold: 5000
    [ 9.629103] adxl372_set_activity_threshold act: 2, ref_e:0 , enable:1, threshold: 100
    [ 9.629435] adxl372_set_act_proc_mode mode 2
    [ 9.630009] adxl372_set_odr odr 4
    [ 9.630977] adxl372_set_bandwidth bw 4
    [ 9.631558] adxl372_set_activity_time_ms act_time_ms 4
    [ 9.631571] adxl372_set_activity_time_ms reg_val 0x1
    [ 9.631779] adxl372_set_inactivity_time_ms inact_time_ms 10000
    [ 9.631790] adxl372_set_inactivity_time_ms reg_val_h 0x3, reg_val_l 0x1
    [ 9.632267] adxl372_set_filter_mode lpf_en 1, hpf_en 1
    [ 9.633420] adxl372_set_filter_settle filter_settle 1
    [ 9.634000] adxl372_set_op_mode op_mode 3
    [ 9.636516] adxl372_spi spi1.0: adxl372_probe ret 0 done
    [ 25.997981] adxl372_set_watermark val: 60
    [ 27.969515] adxl372_set_watermark val: 60
    [ 78.078159] adxl372_write_raw info: 12
    [ 78.078208] adxl372_set_odr odr 0
    [ 78.090871] adxl372_set_activity_time_ms act_time_ms 4
    [ 78.090916] adxl372_set_activity_time_ms reg_val 0x1
    [ 78.091388] adxl372_set_inactivity_time_ms inact_time_ms 10000
    [ 78.091418] adxl372_set_inactivity_time_ms reg_val_h 0x1, reg_val_l 0x81
    [ 78.100169] adxl372_set_bandwidth bw 0
    [ 78.106852] adxl372_buffer_postenable fifo_format:7, fifo_set_size: 3
    [ 78.106888] adxl372_set_op_mode op_mode 0
    [ 78.107899] adxl372_configure_fifo fifo_samples 0x3c
    [ 78.108267] adxl372_configure_fifo fifo_ctl 0x3a
    [ 78.108630] adxl372_set_op_mode op_mode 3
    [ 78.110396] adxl372_set_interrupts int1_bitmask 0x36, int2_bitmask: 0x0
    [ 78.128788] adxl372_accel_irq_handler
    [ 78.129546] adxl372_trigger_handler status1: 0x01, status2: 0x00, fifo_entries: 0

    Regards,

    Terry Cheng

  • 0
    •  Analog Employees 
    on Sep 9, 2019 11:29 AM over 1 year ago in reply to TerryCheng

    Hi Terry,

    It looks that the interrupt is triggered by the data_rdy interrupt. It is being triggered when new valid data is available. This data might as well be 0. Also, that data can also be available in the user data registers, not necessarily in the FIFO. I think that you do not need to enable this interrupt. 

    -Stefan

  • Hi Spopa, 

    I does not enable the data ready interrupt. Why does it trigger?

    LOG:

    [ 78.110396] adxl372_set_interrupts int1_bitmask 0x36, int2_bitmask: 0x0

    Regards,

    Terry Cheng