Recently I came across a topic"Common source stage with current source as load" while going through single stage amplifiers design using MOS. I came across a statement that in Common Source stage, "PMOS is more preferred to used as current source load than NMOS". I would be grateful, if someone please explain me the actual reason of that statement. Kindly mention the reference link if any.
Thanks in advance!!!
Sorry looks like this got overlooked - in a VERY small nutshell, from the perspective of a non-I.C. designer: If you use a PMOS at the "high side" of a circuit node, you'll be "looking into" the drain, which has a higher impedance than the source. That is, the opposite of a source follower, which has a low impedance.
The complement of this is that an NMOS is preferred as a current SINK.
If you want to get a better feel for this idea, make a test circuit in LTspice. Or, build this circuit:
This is the opposite case, using an NMOS as a current sink. And note that LTspice files are provided.
This not the proper forum to answer this question in detail. But the short answer comes from an observation by analog transistor level IC designers that in most IC processes the output resistance i.e. Ro, source to drain resistance in saturation of PMOS is higher than NMOS.
Why is that generally the case you ask? A full answer is beyond what could be discussed here but again the short answer is that MOS transistors are minority carrier devices and the holes (PMOS) have different properties than electrons (NMOS).
I would suggest you read a solid state physics text book for a more detailed explanation ( or take a course in .solid state physics ).