Adalm-Pluto No-OS application developing

Hi everyone,

I'm trying to develope a custom application using no-OS library on zynq with the adalm pluto. My intend is to modify the HDL code, IP blocks and write/modify the C code in order to create a custom application. At this point I did not modify anything about HDL part. I tried to play with the C code provided in the No-OS folder to get different signals at different frequencies, with different bandwidhts, yet i only managed to change the frequency. i changed the AD9361 parameters related with the frequency, bandwidth and attenuation. Only the frequency is changing. Also I tried to change the constant "sine_lut" in dac_core.c to transmit a different type of signal, a chirp signal, yet it didn't work. It seems like i can't write to DMA.

I'm using Vivado 2018.2, programming is done by Xilinx Jtag programmer. Jtag pins on the Adalm-Pluto are soldered to the xilinx programmer's jtag pins.

the code;

main.c;

AD9361_RXFIRConfig rx_fir_config = { // BPF PASSBAND 3/20 fs to 1/4 fs
3, // rx
0, // rx_gain
1, // rx_dec
{-4, -6, -37, 35, 186, 86, -284, -315,
107, 219, -4, 271, 558, -307, -1182, -356,
658, 157, 207, 1648, 790, -2525, -2553, 748,
865, -476, 3737, 6560, -3583, -14731, -5278, 14819,
14819, -5278, -14731, -3583, 6560, 3737, -476, 865,
748, -2553, -2525, 790, 1648, 207, 157, 658,
-356, -1182, -307, 558, 271, -4, 219, 107,
-315, -284, 86, 186, 35, -37, -6, -4,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}, // rx_coef[128]
64, // rx_coef_size
{0, 0, 0, 0, 0, 0}, //rx_path_clks[6]
0 // rx_bandwidth
};

AD9361_TXFIRConfig tx_fir_config = { // BPF PASSBAND 3/20 fs to 1/4 fs
3, // tx
-6, // tx_gain
1, // tx_int
{-4, -6, -37, 35, 186, 86, -284, -315,
107, 219, -4, 271, 558, -307, -1182, -356,
658, 157, 207, 1648, 790, -2525, -2553, 748,
865, -476, 3737, 6560, -3583, -14731, -5278, 14819,
14819, -5278, -14731, -3583, 6560, 3737, -476, 865,
748, -2553, -2525, 790, 1648, 207, 157, 658,
-356, -1182, -307, 558, 271, -4, 219, 107,
-315, -284, 86, 186, 35, -37, -6, -4,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}, // tx_coef[128]
64, // tx_coef_size
{0, 0, 0, 0, 0, 0}, // tx_path_clks[6]
0 // tx_bandwidth
};
struct ad9361_rf_phy *ad9361_phy;

/***************************************************************************//**
* @brief main
*******************************************************************************/
int main(void)
{
Xil_ICacheEnable();
Xil_DCacheEnable();


// NOTE: The user has to choose the GPIO numbers according to desired
// carrier board.
default_init_param.gpio_resetb = GPIO_RESET_PIN;
default_init_param.gpio_sync = -1;
default_init_param.gpio_cal_sw1 = -1;
default_init_param.gpio_cal_sw2 = -1;

gpio_init(GPIO_DEVICE_ID);
gpio_direction(default_init_param.gpio_resetb, 1);
spi_init(SPI_DEVICE_ID, 1, 0);

if (AD9364_DEVICE)
default_init_param.dev_sel = ID_AD9364;
if (AD9363A_DEVICE)
default_init_param.dev_sel = ID_AD9363A;

ad9361_init(&ad9361_phy, &default_init_param);
/*
ad9361_set_tx_fir_config(ad9361_phy, tx_fir_config);
ad9361_set_rx_fir_config(ad9361_phy, rx_fir_config);*/

ad9361_set_rx_rf_bandwidth(ad9361_phy, 15000000);
ad9361_set_tx_rf_bandwidth(ad9361_phy, 15000000);
ad9361_set_rx_lo_freq(ad9361_phy, 1575420000);
ad9361_set_tx_lo_freq(ad9361_phy, 1575420000);
ad9361_set_tx_sampling_freq(ad9361_phy,10000000);
ad9361_set_rx_sampling_freq(ad9361_phy,10000000);
ad9361_set_tx_attenuation(ad9361_phy,0,0);


dac_init(ad9361_phy, DATA_SEL_DMA, 1);
//dac_init(ad9361_phy, DATA_SEL_DDS, 1);

// NOTE: To prevent unwanted data loss, it's recommended to invalidate
// cache after each adc_capture() call, keeping in mind that the
// size of the capture and the start address must be alinged to the size
// of the cache line.
mdelay(1000);
adc_capture(16384, ADC_DDR_BASEADDR);
Xil_DCacheInvalidateRange(ADC_DDR_BASEADDR,
ad9361_phy->pdata->rx2tx2 ? 16384 * 8 : 16384 * 4);

//get_help(NULL, 0);

while(1)
{

}
printf("Done.\n");
Xil_DCacheDisable();
Xil_ICacheDisable();


return 0;
}

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