In case you are curious about the solutions for our June 2021 mini series we posted recently, we present you the solutions for our challenges:
- What protocol do you see here?
The protocol is I2C.
- Identify the lines
Yellow = SDA
Blue = SCL
According to the protocol, SDA (or SDATA) has to go down first. After this, SCL (SClock) is allowed to start. You can clearly see a clock pattern on the line. This makes it easy to identify.
- Why is this protocol not suitable for this setup?
I2C is mostly used for short distances. In this case, you can clearly see the attenuation of both signals. This suggests that the load is too big. The cause for this can be many things, but in this case, the wires were too long. Although the communication is still working, it is not recommended to use it like this.
- What is the small-signal gain of the amplifier in terms of the transconductances and output resistances of M1, M2, M3 and M4?
The small-signal gain depends on the transconductances gm1 and gm2 of M1 and M2 at the input and the output resistances rO1 and rO4 of M1 and M4 at the output. The input differential pair is assumed to be symmetrical, i.e. gm1 = gm2 = gm . The output resistance as seen from node VOUT is equal to rO1 || rO4 . Thus, the small-signal gain Av is given by the expression:
Av = gm * ( rO1 || rO4)
- What limits the bandwidth of this circuit?
The bandwidth is limited by the pole with the lowest frequency.
It is assumed that COUT is the dominant capacitance in the system. Parasitic capacitances related to the MOSFETs are neglected. Therefore, the dominant pole limiting the bandwidth is the pole associated with the output node VOUT. Its contributors are the output resistance rO1 || rO4 and the output capacitance COUT. Thus, the angular frequency ωp of the pole is given by the expression: ωp = 1/((rO1 || rO4) * COUT) .
- What components in the circuit can cause a voltage offset at VIN? Why?
Ideally, the circuit behaves perfectly symmetrical respective to the differential input voltage VIN. When VIN is zero and only a common mode voltage is applied at the inputs, the drain currents of M1 and M2 are the same. In reality, random mismatches in fab production cause M1 and M2 to have different threshold voltages and channel lengths and widths. The same is the case with M3 and M4. Due to this, if VIN is equal to zero, the drain currents of M1 and M2 will usually have different values. To balance out both drain currents, a differential voltage offset needs to be applied at VIN, which is equal to the input-referred offset of the amplifier.
- What change to the circuit needs to be done in order to make it operate as a buffer with unity-gain?
The voltage at node VOUT needs to follow the voltage at the positive input node. In order to achieve this, a negative feedback path from the output VOUT to the negative input node (gate of M1) is required. This is done by shorting VOUT and the gate of M1. Thus, the differential input voltage between the gates of M1 and M2 is regulated to zero. Since VOUT is connected to the gate of M1, the output follows the input with a gain of 1.
- What is a possible implementation of the current source ISS?
The tail current ISS can be generated from a reference current using a current mirror consisting of NMOS transistors. Alternatively, a single NMOS transistor can be used to generate ISS from a known reference voltage. Either way, an additional circuit is required to generate the reference current or voltage.
What is the input capacitance of this circuit as seen from VIN?
In order to calculate the input capacitance, the charge drawn from VIN has to be calculated when VIN changes by a given magnitude. If the input voltage changes by ΔVIN, the voltage at VOUT changes by -G * ΔVIN. The voltage across C changes by (1 + G) * ΔVIN. The charge transferred from VIN to C is given by the expression (1 + G) * ΔVIN * C. Thus, the input capacitance is given by (1 + G) * C . The gain G makes C to appear larger at the input, which is an example of the Miller effect.
- What is the name of the converter topology?
In this topology, the output voltage cannot be higher than the input voltage. The relation between input and output voltage is VOUT= D * VIN. D is the duty-cycle, which cannot be bigger than 1 or smaller than 0. Thus, the circuit shown is a step-down or buck converter.
- VIN is set to 10V. At what duty cycle the converter is switching? What is the average current drawn from the input at VIN in terms of ILOAD? How do they change if VIN is set to 15V?
Assuming that S switches infinitely fast and without power loss, the converter switches at a duty cycle of 50% in continuous mode for VIN = 10V. Since the average power drawn from the input is equal to the average power dissipated by the load, the average input current is ILOAD/2. For VIN = 15V, the duty cycle becomes 1/3 and the average input current becomes ILOAD/3.
- What change to the circuit is necessary to make it operate as an inverting DC-to-DC converter, i.e., VOUT becomes negative?
The upper output node has to be connected with ground instead of the lower output node. When S is closed, current flows from the input to ground through the inductor L. When S is opened, the current continues to flow in the same direction from the lower output node through D and L to ground. As a result, negative charge is transferred to the lower output node, while the upper output node is connected to ground. Thus, the voltage at the lower output node drops below ground, producing a negative output voltage for a positive input voltage.
That's all! We hope you enjoyed our mini series!
Changed font size
[edited by: hschrall at 4:03 PM (GMT -4) on 9 Jul 2021]