In applications that require high dynamic range at sample rates over 250 MSPS. The AD9652 provides the best in class NSD of better than -157 dBFS/Hz at sample rates of up to 310 MSPS.
For more information, visit the AD9652 product page.
The AD9652 uses the HSC-ADC-EVALDZ, FPGA-based data capture board.
For information on the this data capture board, please visit the product page.
For additional information on the AD9652 evaluation board, itself, please visit the wiki page.
I am using AD9652.
and also i set the adc(ad9652) initial as A channel :Normal Mode / B channel : StandBy Mode.
In this operation, when external adc sampling frequency is changed(from 245MHz to 256MHz), adc clock output can not be generated.
I saw the circuit below in AD-FMCOMMS6-EBZ schematic, which is the Evaluation board of the AD9652.
Each lowpass filter is placed on the differential line of the LVPECL signal. I suspect this may have been used to remove the hormonic component in the…
Hello,I want to AD9652 in DC-coupled.
it's possible for this device ? have an example of input schematic to use ?
Thank you for your help
The AD9652 supports sampling rates up to 310 MSPS.
For more information visit the AD9652 product page.
I want to apply an AC-LVPECL clock to the clock input of AD9652.
Figure 62 of the AD9652 datasheet shows how a PECL driver is connected.
As the picture shows, AC coupling capacitors on differential line is placed in front of the ADC input…
I want to apply a AC-LVPECL clock to the clock input of AD9652.
I am wondering how can I optimize it in hardware.
The specifications of applied clock are as below.
Output voltage swing (VOH-VOL)
MIN TYP MAX
620 780 900 (mV)
I want to adjust the voltage of VREF using an external reference.
I couldn't find the specification for VREF in the datasheet.
What is the minimum voltage that can be applied to that external reference (VREF pin) ?