• AD9652: What is the max data rate?

    The AD9652 supports sampling rates up to 310 MSPS.

    For more information visit the AD9652 product page.

  • AD9652: When should I use the AD9652?

    In applications that require high dynamic range at sample rates over 250 MSPS.  The AD9652 provides the best in class NSD of better than -157 dBFS/Hz at sample rates of up to 310 MSPS.

    For more information, visit the AD9652 product page.

  • AD9652:  Which data capture card is used with the AD9652 evaluation board?

    The AD9652 uses the HSC-ADC-EVALDZ, FPGA-based data capture board. 

    For information on the this data capture board, please visit the product page.

    For additional information on the AD9652 evaluation board, itself, please visit the wiki page.

  • RE: AD9652 PN test sequence

    Thank you for your answer.

    According to your file, the sequence is generated using a "Forward Counter Implementation".

    AD9652 datasheet reports a non standard generating polynomial for PN9 (1 + x^3 + x^8), while AN 877 (and provided file dpath_pn9…

  • AD9652 - SFDR performance


    My customer is considering to use AD9652 and they are testing the performance of AD9652 using AD9652 EVM (EVAL-AD9652).

    On this  test, they got bad test result about SFDR values.

    So they need your help for getting better SFDR values.


  • AD9652 Background Calibration


    We need to perform a DC calibration of AD9652. We observed that, after a given time, the digital output code of AD9652 is suddenly altered even though a constant DC voltage is applied to the input of the device. Now, we realized that this is caused…

  • What is the power on sequence for ADC ?

    Hi all,

    I am designing my board using AD9652. I am curious about the power on sequence for AD9652. It needs to be applied four kinds of voltage. I read the datasheet, but I couldn't find any information for power on sequence. Does it not specifically…

  • RE: Question of AD9652 EVB


    The circuit is for the clock input.  It was designed to provide the highest symmetrical clock input from a "filtered" generator source set to a high power level.  CR1 diodes are used for clamping purposes to the the ADC's CLK input is…

  • RE: Simulation model for AD9652


    Unfortunately we do not have a Verilog model.   Please see other thread called "AD9652 ADC tSKEW Min/Max Switching Spec" where we show plot of DCO to Data Skew along with updated specification that will be in next datasheet rev. 

  • RE: AD9652-310EBZ on VC709

    Hi mCezar,

    The AD9652-310EBZ was not designed to specifically work with the VC709 board.  As such, we don't have a Vivado based Xilinx reference design.  The capture board used with the AD9652 is called the HSC-ADC-EVALCZ which uses a Virtex-6 and…