Can you share source code used for benchmarking? I am interested how you got cycle count=1262 for N=512 pts.
Please see Serial Downloader apps note attached:
Hope this sorts you out.
because a lot of these examples were moved from earlier releases of VisualDSP++, you may find that the way the Interrupts are handled by the LDF does not match the more recent default LDFs, such as in this case - the example just has a single block…
Place an SSYNC instruction after you write to DMA4_IRQ_STATUS register (before performing RTI). This would ensure that the peripheral releases the request before the RTI is executed. Another best thing is to perform a dummy PAB access before…
You're right. The RTI noise and the RTO noise are equal for an op amp when you have a voltage follower (unity gain feedback). Otherwise you use the noise gain (1/beta) to translate between RTI and RTO.
Ok, propably should use ISR=>IVT and the title of this thread should be something else too, but don't know how to edit that afterwards,
Right now the problem is around the interrupt handler(s).
What could be the official way of creating one?
I have AD9697, Kintex 7 and AD9528 for clocking. AD9528 works with SI570 (100 MHz base).AD9528 gives me 2 clocks 1200 MHz (OUT0 and OUT 13) for ADC and FPGA.
Alsow AD9528 gives m2 2 clocks 120 MHz (OUT2 and OUT 3) for ADC and FPGA for SYS_REF. Additional…
I have AD9697, Kintex 7 and AD9528 for clocking. AD9528 works with SI570 (100 MHz base).
AD9528 gives me 2 clocks 1200 MHz (OUT0 and OUT 13) for ADC and FPGA.
Alsow AD9528 gives m2 2 clocks 120 MHz (OUT2 and OUT 3) for ADC and FPGA for SYS_REF. Additional clk…
Based on UG-1262 Rev A. page 14, the Digital Die can use the clock of AFE die. I am trying to use the 32MHz HFSOC of AFE die to further increase the processing speed. While trying to activate this feature, CLK CTL0[1:0] = 0x03, the MCU stops responding…