• About the LTM8051 Start-Up Sequence


    I have a question about the LTM8051 start-up sequence.

    Since the LTM8051 has common RUN pins 1&4 and 2&3, is it possible to have a sequence only for each 2ch? (Example: ch1&4→ch2&3)

    Please let me know if there is a way to start…

  • About the IBIS model of LTM8051


    Is there an IBIS model for the LTM8051?
    I would be grateful if you could share it.

    Best Regards,

  • LTM8051 LTSpice Model - VOUT2 and VOUT3 are not outputting


    I am using LTSpice to verify and simulate my design for P/N LTM8051. No matter what I do, I cannot get VOUT2 and VOUT3 to output anything. VOUT1 and VOUT4 operate as expected. 

    • I tried using the macromodel test fixture, which should be setup already…
  • About the internal resistance accuracy of LTM8051


    Please tell me about the accuracy of the internal resistance (249kΩ) of LTM8051.

    Is it 1%?

    I would appreciate it if you could reply.

    Best Regards,

  • LTM8051 Soft Start capacitor vs soft-start time


    For LTM8051, please provide soft-start time relation to the capacitor value connected to the TRSSn pin.

  • LTM8051 for generating 3.3V Vout @ 2A from 3.7V Vin minimum


    We are planning to use LTM8051 for generating 3.3V Vout @ 2A in current sharing mode from 3.7V Vin minimum. LTPowerCAD did not have any excel sheet or simulation for LTM8051.

    Can you confirm whether 3.3V can be generated?

    Also share the LTSpice library…

  • LTM8051

    The part is configured with two pairs of converters. What is the phase angle of each converter in the pair? Are they in phase or 180 degrees out of phase. This is an important parameter and should be in the data sheet.

  • LTM8051 overshoot and soft start


    I’m looking to power an FPGA using the LTM8051. Need to generate the 1.0 volts, 1.2 volts, 1.8 volts and 3.3 volts.

    When I simulate the following circuit using LTspice I have overshoot that I need to limit to less than 1.1 mV.

    Adding a .1uF…

  • RE: PG pin of LTM8051

    Hi Chaz:

    Surprisingly I was just simulating an LTM8051 in LTSpice and the PG pin leakage current there is dramatically higher, approximately 30 uA. Can you confirm this is a bug in the model?

    My first attempt at simulating used 100k pullups and obviously…

  • About RT terminal resistance at the time of external clock synchronization of LTM8051


    Regarding the RT terminal resistance during external clock synchronization of the LTM8051, data sheet P21 states that the Rt terminal resistance should be determined so that the frequency setting is lower than the external clock frequency.

    Is it…