• RE: inquiry about LTM4671 unused output


    You can tie the Run 3 pin to GND and float all associated pins to CH3. 


  • A question regarding LTM4671 parallel 2+2 mode.

    Hi ADI support team. I use LTM4671 in my new design. The datasheet of this device is here: www.analog.com/.../LTM4671.pdf I wonder whether there are two mistakes in the figure2 of datasheet? For 2+2 parallel application, I think PHMODE0 must connect to…

  • LTM4671, setting frequency on 5A outputs

    Hello, dear collegues!

    Could you clear next issue - in LTM4671's description on page 12 it is indicated, so it is possible to increase or decrease the switching frequency

    "FREQ12 (K10): Switching Frequency Program Pin for Both 5A Switching Mode Regulator…

  • LTM4671 tray drawings


    Could you send the LTM4671EY#PBF tray drawings?

    Best regards


  • [LTM4671] Questions about the connectivity of Tsense signals for parallel channels application.

    Hi support team.

    For parallel channels application. How to connect Tsense0/3 pins to the temperature monitor controller? 

    The diode connected NPN transistor across the TSENSEn+ and pin and TSENSEn- pins can be used to monitor the internal temperature of…

  • LTM4671 OUT1 & 2 (5A output ch) efficiency

    We are considering using OUT1ch with 12V input 0.8V 2A output.
    With efficiency near the data sheet (12V input 1V 2A output)
    I looked at the efficiency calculation result in LTpowerCAD.

    The two were quite different.
    Q1: Do I understand that the data sheet…

  • Question about LTM4671


    I have three questions about LTM4671. Could you take a look at the attached file?




  • Inquiry about a Pin Connection of LTM4671


    I'd like to ask about a Pin Connection of LTM4671.

    (1) If I don't want to use a temperature monitor, I can connect TMON to INTVCC12.

    In that case, how should I set the following two pins?



    (2) The following…

  • LTM4671 SS pin


    I'm a DFAE in Japan. Our customer evaluates LTM4671 on his trial pcb. The start up time of 5A ch is too long for him and he deletes the capacitor between TRACK/SS pin and GND. I think it possible because there is an internal pull-up. Is it correct…

  • The problem about the parallel output of LTM4671

    hi all:

    Now I am using LTM4671 to generate three power supply for FPGA: 1.2V, 2.5V and 1.8V; the configuration of the LTM4671 is as follow:

    VOUT0: 1.2V

    VOUT3: 2.5V

    VOUT1 and VOUT2: 1.8V

    My circuit schematic is refer to Figure 31 of the datasheet.