• LTC6954: Startup


    from the datasheet i would excpect the LTC6954 to have an active output after power up without further programming. Is this correct?
    However, in measurements without programming I was not able to detect any output. Are there some typical mistakes…

  • RE: LTC6957 parallel clock tree

    Hello Chris,

    thank you very much for the plot of the LTC6955.

    I can't precisely specify phase noise requirements because of proprietary stuff but we can communicate it through email if you want.

    Do you have a phase noise specification of used Pascal…

  • RE: Clock buffer for AD9684

    How many parts are you fanning out to?  The AD9508 is a good part as is the LTC6954.  

  • RE: LVDS and LVCMOS output clock in phase

    Hello Gerrit,

    You may want to look in our clock generation devices link.


    In here I would look at some of the devices with lower frequency …

  • RE: Can I use HMC6832 for LVDS data clock fanout?

    That is correct the internal input capacitors will cause an initial CM ramp if you go from a DC signal to a AC signal.  Some of the LTC6954/55/57 buffers do not have this input cap, but the common modes do not necessarily line up with LVDS.  So maybe you…

  • RE: Divider-by-3 duty cycle

    Hi Gil,

    The /3 of the HMC794 does produce a 50% output.    However, it looks like your 25M-100M input frequency is below the HMC794's min input frequency

    R Counter outputs are typically not 50%. 

    You can also look at the LTC6954.  This device has a /3…

  • RE: Clock tree with LTC6951 as reference and LTC6952 as clock distribution in parallel sync?

    I think to answer this question fully I will need to understand your reference frequency, how many clocks and SYSREFs you need, and your clock frequencies.  From your description, I'm not exactly sure what you is being asked.

     Usually you want a ultra…

  • Clock problem with ADCLK925 and AD9695/AD9739


    I am using AD9695 and AD9739 with an ultrascale FPGA, on custom board.

    We have no problem with the design, until we load a high consumption bitsream into the FPGA.

    When the a full FPGA is loaded, the input clock (1280MHz) is no longer detected by…

  • RE: Help with LTC6957-3 singal integrity question!

    LTSpice has a generic transmission line component called Tline, shown below.   The feature allows you to program the delay of your 0.6" transmission line.  For a quick calculation to determine the delay I would assume 6ps/mm delay, this calculates to…

  • RE: Multicard Synchronization

    Application Note 165 is a good starting place.  

    The big question is are you generating and distributing the 500MHz  clock on one board and then distributing that to your other cards.  Or are you sending a reference frequency from one board to your other…