• LTC6952, LTC6953: SYSREF Pulse Mode schematics with AC coupled interfaces

    How can I interface the LTC6952, LTC6953 CML common mode level (~2.3V) to devices that require common mode levels <2.3V?

  • RE: LTC6952Wizard

    In case of LTC6951, AN161-1 describes the detailed frequency setting method. Is there any document similar to AN161-1 for LTC6952? I found the setting method is not easy. Can I refer to AN161-1 for LTC6952 setting?

  • HMC7044 or LTC6952

    I would like to know if I can use multi stages HMC7044 or LTC6952 for multi ADC clocking.

    I want to synchronize 1800 * ADC at 400MSPS.

    Skew less than 100ps

    Jitter to minimize ADC SNR impact < 100fs

    Can I reach these constraints with 4 stages of HMC7044…

  • AD9162 DAC Clocking solution above 4.5GHz using LTC6952.


    I am looking to use an AD9162 high speed DAC.

    In order to generate the system clocking architecture we are looking to use an LTC6952.

    It is understood how we can achieve deterministic latency in the JESD204 link if the DAC clock is less than the 4…

  • RE: ParallelSync operation of LTC6952

    HI Andy,

    I believe this is the same issue we worked through together via email.  Sorry I didn't notice the post on EngineerZone until Del tagged me.  For history's sake on Engineering Zone, I'm copying/pasting my last email I sent to you below.…

  • RE: HMC7044, HMC7043 vs LTC6952, LTC6953

    Thanks for your answer! The reason why I pick LTC6952 is that it can operate in very high frequency. As for AD9528,is I want to use AD9528 for AD9371. In the meanwhile,I want to make all clocks in my system operate from a same sourse.So,I use LTC6952 as…

  • Clock tree with LTC6951 as reference and LTC6952 as clock distribution in parallel sync?

    Wondering if it is possible to use the LTC6951 internal oscillator as reference to the LTC6952? The LTC6952 function as clock distribution for multiple JESD ADC and DAC.  I do not want to use an external clock for this clock tree architecture. Nor do I…

  • RE: HMCAD1511 with CML clock

    According to the HMCAD1511 datasheet differential sine inputs must be at least 0.8Vpp.  The LTC6952 typical CML output is 420mVpeak, oso peak to peak will be over the 800mV threshold. The minimum output level of the LTC6952 is 320mVpeak, so if you are…

  • RE: Low phase noise clock generation (16@1.6GHz, 2@200MHz) from low phase noise 100MHz source

    As of May 18,2019 our lowest phase noise multi-output clock ICs at 1.6GHz are the LTC6952, HMC7044 and LTC6951 (in that order). 

    Here is a comparison table of the LTC6952 and HMC7044, these are probably the 2 chips I would look at first.  


  • LTC6952 Cleanup Loop Example (Reference Jitter Cleaner)

    Below is an example of the LTC6952 as a cleanup loop and reference distribution.  

    Here is a pic of the register settings