The LTC6950 would be a good clock driver for the LTC2000. It would also work with the ADN4650.
For VCXO 122.88MHz application. Could you share with customer the design guide for PLL test?
(ADF4002 & LTC6950 )
I am using the AD9637BCPZ-80.
I have to shift the VCM down ~ neg 0.9VDC in order to accommodate a positive gaussian pulse of ~2V p-p amplitude.
The CLK +/- pins for the AD are driven by the LTC6950 PLL set to 8x the input clock (AC coupled).
Why can I not achieve datasheet additive(residual) phase noise performance at frequencies <350MHz with the E5052 phase noise analyzer?
In fairness to the E5052, we have seen the same issue discussed below with other vendor's phase noise analyzer's.…