• 使用LTC6804-2监视电池电压时，是否会出现某时刻电压采集不到

    Dear

           在使用LTC6804-2的是否会出现某时刻电压采集不到，然后寄存器显示一个XXXX的数值，这个XXXX的数值和不接电池读取的数值相同，是否会出现这个情况一般怎么处理，目前处理方法是判断一下采样值是否为有效值.

  • LTC6804-2 not responding to RDSTATA command. No data is returned. While RDSTATB is working without any issue?

    I am using LTC6804-2 in one of our products. The MCU is connected to the LTC6804 directly through SPI (ISOMD tied to V-). I have ported the sample Linduino code on Analog.com website to my application written in C, and made appropriate changes to make…

    • ADSTATImplementation.txt.zip

  • RE: LTC6804 异常的GPIO1读数

    GPIO1 can be affected by MUX shoot through glitches. The best workaround is to do a dummy conversion of just GPIO1 (don't bother with the read and it can be the fast filter mode), then do the GPIO conversions. Note that with un-buffered 100k sensors there…

  • LTC6804芯片SPI唤醒的问题

    你好，我想咨询下LTC6804芯片SPI唤醒的问题，初步打算采用4线SPI（ISOMODE=V-）。VREG的输入由LT3990芯片提供，芯片的EN/VVLO通过DRIVE驱动 实现LTC6804低功耗。
    1，在手册 POWER CUMNSUMPTION 那个章节 里边写了ISO SPI接口供电是由 VREG提供的，,那四线SPI实现唤醒 他的供电是否与VREG有关系，即VREG为0是否可以唤醒四线spi电路 进而唤醒CORE电路？如果采用ISOMODE=VREG模式，在VREG=0即ISO SPI未供电的情况下…

  • LTC6804-2.APP程序中free()函数和malloc，找不到相应函数，编译老是错误，啥原因？

    free（）函数在哪里能找到原型。

    编译时老是显示如下 错误：

    Building configuration: YWYJYSJ-20190506 - Debug
    Updating build tree...
    Linking
    Warning[w6]: Type conflict for external/entry "free", in module LTC68112 against external/entry
    in module ?free; prototyped function…

  • Pluto - 2 Rx and 2 Tx using MATLAB

    Hi,

    I would like to setup the SDR Pluto to operate in 2 Tx and 2 Rx mode.

    I have followed the steps in the following video : https://www.youtube.com/watch?v=ph0Kv4SgSuI

    However, I am unsure how to setup and control the 2nd transmitter or receiver. 

    …

  • RE: ADA4940-2, issue on creating 2 differential signals around 0V

    Hi, 

    With a bit late, thanks for this suggestion.

    By applying -0.2V to R3, this circuits can convert 0 to 0.4V to a balanced -0.2 to 0.2V .

    It has been checked on the eval board.

  • ADV7611 YCbCr 4:2:2 SDR issue

    I am trying to configure ADV7611 to output 1280x1024 video in 16-bit SDR ITU-R BT.656 4:2:2 Mode 0.

    In free-run mode with blue background I get "0xFF00, 0x0000, 0xFF00, 0x0000..." pixel data, but it is 1280 LLC-period wide DE window between HSyncs…

  • A question regarding LTM4671 parallel 2+2 mode.

    Hi ADI support team. I use LTM4671 in my new design. The datasheet of this device is here: www.analog.com/.../LTM4671.pdf I wonder whether there are two mistakes in the figure2 of datasheet? For 2+2 parallel application, I think PHMODE0 must connect to…

  • ADF4372 Fs/2 and 3Fs/2 Clock Spurious

    Hello ADI Team,

    I am using ADF4372 PLL for generating Output Clock with frequency 12.288 GHz in Doubler path (RF16).

    PLL Settings:

    Reference input frequency is 409.6 MHz.

    PFD frequency = 307.2 MHz

    VCO Frequecny = 6.144GHz

    PLL Output Observation:

    I observed…