• AD9914/15, registers for Programmable Modulus


    In Programmable Modulus, where are the A and B registers? I can't find them specified anywhere in the datasheets.

    Best regards


  • ADN2913/15 and spread-spectrum clocks


    I'm trying to confirm if ADN2913/15 are suitable for use with spread-spectrum clocked data streams (transfer bandwidth seems sufficient, however, datasheets do mention a 1000ppm loss-of-lock threshold)

    For example, would a 5Gbps data stream clocked…

  • AD99114/15 power supply sequecing


    Is there a power supply sequencing requirements for the AD9914/15? how long do these devices survive with just +3.3V on and +1.8V off and vice versa?



  • ADL5375-15 sideband suppression and other

    Hi All,

    One of my customers is using ADL5375-15 Quadrature Modulator for his prototype board.

    High-Speed DAC generates analog I/Q signal and is fed to ADL5375-15 through reconstruction filter designed by him.

    Attached file “SSB-compression” shows sideband…

  • ADSP2126x FLAG10-15 thru DAI

    Hi all,

    I read that the FLAG10-15 signals can be routed through the DAI when the parallel port is enabled.

    What happens when the parallel port is disabled and these flag signals are routed through the DAI?

    Like this:

    1. Enable parallel port
    2. Route…
  • Socket for ADuC7038 (CP-32-15)

    Hello Everyone,

    I need an SMD socket which I can solder onto a PCB to allow quick exchange of uC's.

    Could you please help me to find one?

    Thank you in advance.

  • ADL5375-05 vs -ADL5375-15

    Which is the better for lowest spurs -the 0.5V biased ADL5365-05 vs. the  1.5V biased ADL5375-15?

    I am driving the ADL5375 IQ mod with ADF9788 DAC,  fixed LO freq =900M, with internal DAC DDS set  to 150Mz. The data rate is 225M for Instantaneous BWidth…

  • AD9914/15 IO_UPDATE and SYNCIO clarification?

    What is the minimum pulse width of the SYNCIO signal in order to reset the serial interface communication?

    Does CS need to be asserted (low) for SYNCIO to have effect? (would be natural, but the information is missing from the DS).

    If IO_UPDATE setup…

  • RE: about ADI IP code axi_ad9361


        sorry,it is axi_ad9361 ip .Whether util_upack IP divides dac_data[63:0]={I0[15:0], I1[15:0], Q0[15:0], Q1[15:0]} into I0[15:0], I1[15:0], Q0[15:0], Q1[15:0],Whether  the correspondence of dac_data[63:0]={I0[15:0], I1[15:0], Q0[15:0 ], Q1[15:0]} is…

  • About ADRV9009 TX JESD204B IQ Data Sequence.

    Here is the dac two steps crossbar of adrv9009 chip. (image1)
    we select the jesd204b deframer configuration(M = 4, L = 4, S = 1). (image2)
    we set taliseJesd204bDeframerConfig_t.enableManualLaneXbar=0
    The Rx ADRV9009 JESD204B DeFramer Configuration (M = 4…