有谁开发过这款芯片?目前调试的现象是22位的no latency output 有输出，但24位的滤波结果没有输出。MCLK=1Msps，DF=4，每个转换周期都有busy信号，drl信号每隔85ms周期被拉高一次（与手册描述的每隔DF个转换周期拉高一次不相符），在drl信号下降沿后给scka信号，并没有数据从sdoa引脚输出。驱动时序已经按照手册要求写的，并有检查无误。
In ADC LTC2512-24 datasheet, LT6202 is recommended to be used as ADC driver. But in "Precision ADC Driver Tool - BETA", there is no option to use LT6202 in driver selection (only LT6200 available). In this ADC driver tool, ADA4807-2 seems to…
1. I use the LTC2512-24 digital filter to output SDOA, and the sampling data has a delay;2. According to the manual, use SDOB without delay output, but there is still delay in sampling data.Thanks Reply!
I am considering both the LTC2512-24 wideband FIR filter SAR and LTC2380-24 narrowband SINC1 SAR for a design which is to have both good AC as well as DC specs. What is the passband ripple of the LTC2380-24?
If you look at Figure 22 on page 25 of the LTC2512-24 data sheet you will see that a total of 35 cycles are required for full settling of the filter. This is fixed in this device and cannot be changed.
Hello, I applied LTC2512-24 design acquisition circuit, FPGA driver chip, DF=4, MCLK=1MHz, SDOA output, but the chip can only work for a while at a time, need to restart the power to work again, but also work for a while。
I also met the same question. How did you deal with it later?
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tDRLLH, tBUSYLH, tDSDOA and tDSDOADRLL will not change with clock frequency.
The specifications for the ADC Timing Characteristics Table are:
Hi there, I am looking for simplified 24-bit RGB to CVBS encoder IC in ANALOG DEVICES product line. Could you suggest one preferably that has EVAL board with a detailed instructions. My input signal is sourced from DVI receiver TI TFP401