• LTC2380-24 Figure11b condition


    In LTC2380-24 datasheet, 

    Which setting is used in LTC2380? (How ns is acquisition time?)

    With Precision ADC Driver Tool,

    ・ADC Driver is LTC6363(short circuit current is near LTC6362).

    ・fin=2kHz Rext=35.7Ω Cext=6.8nF Sample Rate =2MSPS Vref=5V…

  • Ask questions about LTC2380-24 ADC Driver design


    Here is an example of LTC2380-24 ADC Driver design, I will have some questions to ask.

    a. Based on LTC6363 datasheet, the settling time is 720ns(to 4ppm), on the other hand, the RC time constant is τ=R6*C6=60.4*33=1993.2nS. But

    the acquisition…

  • Passband ripple of the LTC2380-24?

    I am considering both the LTC2512-24 wideband FIR filter SAR and LTC2380-24 narrowband SINC1 SAR for a design which is to have both good AC as well as DC specs.  What is the passband ripple of the LTC2380-24?

  • 2289A-B with LTC2380-24


    I work with demo circuit 2289A-B and the LTC2368-24 but i would change it to LTC2380-24, is it possible? Or may I change anything else on the demo bord ?

    Kind regards


  • RE: Need for external FIR + Decimator to improve SNR with this chip?

    The LTC2380-24 uses the same SINC1 filter for all values of N

  • RE: LTC2380-24 Distributed read of averaging 8

    Hi steven55,

    SCK should be toggled only after BUSY has fallen. The data sheet states that During power-down, data from the last conversion can be clocked out. Power-down occurs after BUSY goes low. Clocking out data during a conversion can potentially…

  • RE: LTC2380-24 Distributed Read: Averaging 2 Samples


    Skipping the steps 5-8 will lead to 24 SCK pulse which is what the LTC2380-24 needs to output the 24 bits conversion results. You can check it on the timing diagram page 10 of the datasheet.



  • How to synchronize two LTC2380-24 boards?


    How two ADC LTC2380-24 ADCs can be synchronized so that the sampled data from the ADCs are phase aligned ?

    Thanks a lot in advance for your help !



  • RE: ENOB after decimation

    The LTC2380-24 without any averaging only has an SNR of 100dBFS. This is a little more than 16ENOBs. 24bits of resolution should still adequate after downsampling by 24X.

  • RE: Are you planning an ADAQ uModule with 2MSps at 16 bit or > 100Kps at 24 bit?

    On behalf of Ryan Curran.
    We currently don’t have a product in development that would meet either criteria, though both areas (higher speed and higher precision) are product spaces that we are exploring.  I would certainly be on the lookout for uModules…