The LTC2324-16 data sheet is being revised. Table 2 will be changed as shown below
The LTC2324-16 demo board (DC2395) has an onboard FPGA that deserializes the data before transferring it to the DC890. The DC890 has limited memory and a slow USB interface chip that would make real time data capture impossible at the data rate that the…
In LTSpice, the current drawn from VDD pin about 8A when LTC2324-16 is used in CMOS mode. What is the nominal current for OVDD and VDD pin when it is in CMOS mode and all channels are used in 2Msps?
I've got a few questions about the LTC2324-16 ADC.
This device does not appear to have an output that indicates that the conversion is complete.Therefore I am assuming that we start the conversion with a pulse on /CNV and just wait around for some…
I hope that I'm in the right place
I have a question regarding the Linear LTC2324-12:
I'm using the internal reference (my case is 2.048V) - can I use REFOUTx as an input for resistor division? please see the attached file configuration?
I take the example of the 4 Channels ADC LTC2324-16. The sampling rate is 2Msps/Ch ( and there are 4 ch) in total 8Msps * 2 bytes = 16MBps. that should be respected between the ADC Board and control Board.
If the control Board is buffering the data then
LTC2324-12 Datasheet Page 5 Line:
tCYC Time between Conversions (Note 11) tCYC = tCNVH + tCONV + tREADOUT min 0.5us max 1000us
and Page 6 Note 11:
Note 11: Guaranteed by design, not subject to test.