I drive  ltc2323 at 5MSPS rate with fpga code  ,and refer to the driven code which ADI offered.but there is a big porblem:the timing of signal sck and cnv signals are right and comply with the spec ,but I can't get back the adc value no matter what I d…

Hi Gentleman, 

Could you please detail LTC2323-14 TDSCKCLKOUT spec?

Why we do only have a minimum value in the datasheet? is there a spec for Maximum Values or is it related to a variable timing depending on application that cannot be measured?

Thank…

Hello,

I'm trying to simulate the ADC-LTC2323 16bit in LTspice in order to measure THD value of this converter and compare it with the datasheet. The model of the LTC2323 is available in LTspice. I'm connecting two sine signals to the differential inputs…

Hello,

We are controlling the LTC2323 from FPGA and we want to sample the data with 5 MSPS ind LVDC mode.

In the datasheet (last page) it is somehow written, that for the CNV pin a additional FlipFlop should be used.

But why? What would be the advantage…

Data sheet says " A 105MHz external clock must be applied at the SCK pin to achieve 5Msps throughput. ". what should I do to use this ADC with different sampling rate , e.g. 3.125 Msps? 

你好，ADI工程师，最近选型多通道同步采样AD芯片，要求是精度12bit，采样率在5M--40M之间，现在看到 产品分类有两种：一种是LT2323-12 ，标明是同步多通道采样AD，另一类AD9637只是标明多通道，我看了AD9637的数据手册，它应该也能8通道同步采样。现在有两个疑问是：（1）LTC2323-12 和AD9637同步采样有什么差别？为什么AD9637不标明是 同步 多通道采样芯片。（2）AD9637-40，手册上标明CLK最小输入时钟是10M，如果输入5M时钟，芯片还能用吗？性能损失多少…

你好，ADI工程师，最近选型多通道同步采样AD芯片，要求是精度12bit，采样率在5M--40M之间，现在看到 产品分类有两种：一种是LT2323-12 ，标明是同步多通道采样AD，另一类AD9637只是标明多通道，我看了AD9637的数据手册，它应该也能8通道同步采样。现在有两个疑问是：（1）LTC2323-12 和AD9637同步采样有什么差别？为什么AD9637不标明是 同步 多通道采样芯片。（2）AD9637-40，手册上标明CLK最小输入时钟是10M，如果输入5M时钟，芯片还能用吗？性能损失多少…

Hi hi

I'm starting a new project with the following specs

1 - 16 analog audio inputs 
2 - 16 analog audio outputs 
4 - Matrix mixing capability 
5 - Uses SigmaStudio 
6 - Minimum sample rate = 96 KHz

Which DSP chip would you recommend?

Is ADAU144x my best…