Hello, 

I'm using ADC board LTC2320-16  ( https://www.analog.com/cn/products/ltc2320-16.html#product-overview ) with control board DC890B  (https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/dc890b.html#eb-ov…

DEar Support Team,

I have a question regarding the SRD#/DDR pin (pin 23) of the LTC2320-16:
According to the datasheet, this pin should be tied to GND or OVDD. Is it also possible to control this pin from an FPGA?
When driving the pin from an FPGA, the…

Hello,

I have a question regarding the SRD#/DDR pin (pin 23) of the LTC2320-16:
According to the datasheet, this pin should be tied to GND or OVDD. Is it also possible to control this pin from an FPGA?
When driving the pin from an FPGA, the SDR#/DDR pin…

LTC 2320-16 SDR clock out does not  frequency to 105Mhz.

In my application only using 82Mhz, but number of clock out does not match 16. and gen out freq also not matching 82Mhz.

Hi all,

I would like to know if you can recommend any  LVDS digital isolator for the ADC LTC2320-14. I am going to use a CLK_F of 50 MHZ to achive approx. a conversion frequency  of 900 Ksps. My problem now is  I cant find the relationship between the ADC and…

Hello,

I try to config sports work on 16-in and 16-out IIS mode, i can not file demo source from the EV-2156x_EZ-KIT. 

I try initial-code like below, but it did not work.

eResult = adi_sport_Open(SPORT_DEVICE_0A,ADI_HALF_SPORT_A,ADI_SPORT_DIR_RX, ADI_SPORT_I2S_MODE…

Hello, we have an application where we need 12 channel ADC. We have a Microprocessor that can do 32Bit TDM 8 (256BCK per frame).4

Is there a way I can combine 3 ADAU1772 (we are hoping to use this part since we are already using it in other products) to…

Hello! I would like to ask about the CLKOUT pin of ltC2325-16 chip, the signal on this pin is said to be the delay of SCK signal in the reference book, then how is this signal generated? When THE SCK signal is generated, the chip will automatically delay…