• RE: How to properly and passively clock two ADCs from single encode clock source?

    What is the clock being generated by?

      The LTC2268 also comes in a quad (LTC2175) if you need four channels all synchronously sampling, that might be a better option. 

  • 2011-01-10 14:14:47     workqueue

    2011-01-10 14:14:47     workqueue

    Chris Brissette (UNITED STATES)

    Message: 97302   

    I have been hunting a random lockup, happens about once a week. Seems like it has something to do with the using the ttybf1 uart.  I have been looking to where workqueue…

  • [LTM9006-14]

    The Vcm on My Demo board DC1751 doesn't have output,is it wrong?And what the output type of FR and DCO ?LVDS?

  • ADF4356 for ADMV1013/14

    Hello,

    I am using ADF4356 for ADMV1013/14. I just found out the max RFOUT power for ADF4356 is -2 dbm at 6.8GHz. ADV1013/4 requires LO input is within -6 to 6 dbm. What will happen if LO power is less than -6dbm? Let's say LO input at ADMV1013 only sees…

  • LTC2153-14 CLKOUT

    Hi,

    My customer is planning to employ LTC2153-14. Here are my customer question.

    (I don't have demoboard now. please tell me.)

    Q1)Input CLK signal to ENC PIN after power-on. We would like to know the CLKOUT PIN condition.

    What Is the default condition…

  • LTC2314-14 not working

    LTC2314-14 is not working. Only zeros coming on SPI. I am using STM32L431RBT6 as SPI master at 8MHz.

    I used the following code:

    HAL_GPIO_WritePin(GPIOA,GPIO_PIN_4,GPIO_PIN_RESET); // CHIP SELECT PIN 
    HAL_Delay(5);

    HAL_SPI_Receive(&hspi1,(uint8_t *)&buf…

  • LTC2258-14 No output or CLKOUT

    We are trying to use the ltc2258-14 with the serial programming mode, Double data rate CMOS.  We can not get any output on the clkout line or any of the data lines.  We have also been unable to read any of the mode registers.

    Any thoughts as to why we wouldn…

  • RE: 14-bit DTS

    This question has been closed by the EZ team and is assumed answered.
  • LTC2256-14 hold time

    Hi,

    Could You please clear some things for me:

    The datasheet for the device stated that the conversion starts at the rising edge of ENC+ signal.

    Is the sample-hold internal capacitor fed with input signal during whole high time of ENC signal or for some…