Is there a fixed phase relationship between the sampling clock input(CKP/N) and the internal divider output(DCKOP/N) after each power-up of the LTC2000?
If it is fixed, what is the phase difference?If it is not fixed, will this clock be used as the reference…
Can anyone get the picture of ltc2000 register map from LTCDACGen? I have no adapter that's why this menu is inactive. Is it possible to make this menu active without adapter? Thanks.
Hi! I have problem iwth using ltc2000-16. SFDR = 47dBc(fout = 270MHZ, fdac=1200MHz) Rfsadj = 500Ω, Rload = 12,5Ω, LIN_DIS = 0, LIN_ GN = 75%, power is fine. What's the matter?
I have not yet made the schematic. First I want to understand how I can load the LTC2000's TSTP/TSTN pins.
We take this measurement by toggling the output between two codes and looking at the output with a very high speed scope. From the scope shot we can see where the DAC settles to the 16 bit level.
When using JESD, are the DACs (e.g. AD9163 and AD9164) going to have issue if we start to shift the phase of the clock? If so, is LVDS a way around this (e.g. LTC2000)? We are thinking of shifting the clock by about 50ps for equivalent time sampling.
In datasheet on page 30 described "Measuring LVDS Input Timing Skew".
For example, to compare DB15P/N to DCKIP/N, first write 0x60 to register 0x18 to set LMX_EN = 1, LMX_ADR = 10000, and LMX_SEL = 0. The signal from DB15P/N will be driven…
I have a customer who has a 4DSP - FMC230 board with the AD91219 on it.He also has purchased a Xilinx Virtex 7 board which he connects the board to. He is wondering if there is software where you could load Amplitude, Period , duty cycle, slope, and it…