• LTC1569-7  Non-aliasing phenomenon的非混叠现象

    LTC1569-7 shows half of the amplitude of the input signal at 8 times the cutoff frequency. 
    What is the reason?

    LTC1569-7在截止频率的8倍处出现了输入信号幅值一半的现象,请问是什么原因?

  • RE: LTC1569

    Hi,

    There are two LTC1569, LTC1569-7 and LTC1569-6. The data sheet for each IC lists the typical clock feedthrough for Vs=3V. The clock feedthrough for self-clocking at  Vs=3V for the LTC1569-7 and LTC1569-6 is 0.4VRMS and 0.1VRMS respectively. The clock…

  • LTC1569-6

    I use LTC1569-6 with external clock. But periodically, I want to stop external clock and set at pin DIV/CLK "0" signal from microcontroller. Is it correct?
    As I understand, in this case the DC offset will increase. Will this DC offset be stable…

  • ADF4360-7 Evaluation Board Software for Windows 7

    Hello,

    I tried to install the ADF4360_V301 and also ADF4360_v2_0 on windows 7 32-Bit.

    both of them failed to run:

    V2_0 showed Run-time error '53': File not found: parllio

    I guess the printer port for the serial connection can not be initialized…

  • cp_vid_std[7:0] (IO Map, Address 0x05[7:0]) of ADV7480.

    Hello,

    I have questions about register cp_vid_std[7:0] (IO Map, Address 0x05[7:0]) of ADV7480.

    We think we don't have to change cp_vid_std according to HDMI input resolution.

    Your S/W driver(SRC-Rel1.5.0_BETA) seems to set cp_vid_std to "0x53"…

  • RE: AD9697 and Kintex 7 SYNC problem

    please refer to DETERMINISTIC LATENCY and MULTICHIP SYNCHRONIZATION sections of the datasheet. the sysref frequency should be an integer divider of internal LMFC

  • RE: [ADV7280A] Saturation register (SD_SAT_Cb[7:0] (Address 0xE3) and SD_SAT_Cr[7:0] (Address 0xE4))

    Hi Tamu-San,

    Do you mean the (0xE3,0XE4) registers indicate following specification?

             Yes, Saturation register values represent what you have intimated in the above graph. it seems saturation increases the gain is also increasing.

        Could you please crosscheck…

  • RE: AD9697 and Kintex 7 JESD connection problem

    if the ADC's JESD204B pll is locked, then the issue most likely is on the fpga side

  • RE: LTC3350’s application circuit 7 ( the datasheet page 43)

    Yes and no. The falling edge turns off the FET which adds the 1MΩ resistor but the filter is in place as PFI is rising. We said falling because it turns adds the R of the RC filter on the falling edge. 

    Best Regards,

    Marty

  • Amplifier LTC6019-7 related problem 咨询关于LTC6019-7这款程控放大器的问题

    LTC6910在单5V供电工作状态下,其输入时钟可否大于3MHZ,或者说在单5V供电的工作状态下,其-3dB截止频率可否高于150HZCan the input clock of LTC6910 be greater than 3MHZ under the single 5V power supply working condition, or can the -3db cut-off frequency be higher than 150HZ under the single 5V power…