Although I have found the statement in the subject (video inputs accept logic levels from 1.8 V to 3.3 V) in the datasheet and elsewhere, I do not see how to do this.  The only electrical specifications I can find seem to indicate that the IO voltage can…

Hi,

I'm looking for a device that is capable of translating 1.8/3.3v to 3.3v.

The problem is, the circuit should be able to determine the i/o level and choose the supply voltage for translation.

Dear Sirs,

I was looking at the  AD9914 eval board schematic and Gerber files, and I had a question about pin 57. of the AD9914, AD9915.

The data sheet seems to show that pin57  is AVDD, one of three pins for Analog Core Supply 1.8v.

In the evaluation…

ADG3247 支持1.8到3.3升压的电平转换么   速率支持500MSPS

I Have a 1000M Enthernet   Phy with 2.5 level  the FPGA IO is fixed  1.8V .      so  need a level Translation chip for all TX/RX CLK

The  clk up to 125Mbps . time rise 1ns.

could you please recommend one ?

Thank you very much.

What is the best way to interface 2 ADAR7251 chips to an ADSP-21573 so as to allow the maximum sample rate of 1.8 MS/s?

What is the best way to interface 2 ADAR7251 chips to a BF707 so as to allow the maximum sample rate of 1.8 MS/s?

Hi all. I cant start working with ad9954 on my own board. Crystal quartz Geyer KX-13T 25 MHz with 40 pF loads. CLKMODESELECT connected to 1.8 V. But on the oscillograf there is nothing (25 MHz) on the REFCLK inputs!  Thank you.