I would like to ask you for my new ADC design: LTC1407
I have a requirement of 500kHz BW with 100dB gain. I would like to have differential input and output.
DS provides an OP amplifier as a suitable driver. However, I need to fullfill…
I'm using an LTC1407-1 in my prototype. The specs say the frame length is at least 32, typically 34-bits wide.
Based on the drawings, I figured out how to communicate with the part in 34-bit mode, it works correctly.
But it is extremely unclear…
I know the LTC1407-1 is fully specified up to the maximum throughput/channel of 1.5 MSps. Would there be any drawback in performance if it were pushed to 1.536 MSps?
If you look at the LTC1407 timing diagram on page 9 of the data sheet you will see the SDO output goes into a Hi-Z condition after 16 clocks. That is why SDO goes into levels between high and low. This is normal. Using 32 clocks at the low speed you are…