I would like to ask you for my new ADC design: LTC1407
I have a requirement of 500kHz BW with 100dB gain. I would like to have differential input and output.
DS provides an OP amplifier as a suitable driver. However, I need to fullfill…
I know the LTC1407-1 is fully specified up to the maximum throughput/channel of 1.5 MSps. Would there be any drawback in performance if it were pushed to 1.536 MSps?
Clocks 33 and 34 are required in order to satisfy t7 when running SCK at its maximum rate. If running a slower SCK frequency as long as t7 is satisfied only 32 clocks are required.