• RE: LT1761MPS5-3_3 LDO min load req

    There is no min load requirement for LT1761. The issue may be about stability.  Please make sure you get the schematic right and follow the PCB layout guidelines. Available demo board may be of help.

  • LT1761 LDO Regulator Failure Modes

    What is the behavior and  failure mode of the LT1761 when operated close to and above its junction temperature?

    As the max junction temperature is approached and exceeded, what is the effect on the output voltage. 

    Is it possible for the part to become unstable…

  • RE: REFERENCE DESIGN FOR AD9653BCPZ-125

    Please find the attachment missing in the last email.

    regards

  • ADF4360-0 can not lock

    I used adf4360-0 to synthesize a 2.5GHz clock, but the clock can not lock. the schematic, ADISimPLL simulation file and register configuration values are attached.

    The 3-wire interface is controlled by a FPGA, and the interval between the control latch…

  • TAGS LIST: Power by Linear

    LTM8045
    LTM8049
    LTM4651
    LTM4661
    LTM4686
    LTM4676
    LTM4686-1
    LTM4676A
    LTM4675
    LTM4677
    LTM4678
    LTM8062
    LTM8061
    LTM8052
    LTM8026
    LTM8056
    LTM8064
    LTM8054
    LTM8055
    LTM4600
    LTM4600HV
    LTM4608A
    LTM4604A
    LTM8032