There is no min load requirement for LT1761. The issue may be about stability. Please make sure you get the schematic right and follow the PCB layout guidelines. Available demo board may be of help.
What is the behavior and failure mode of the LT1761 when operated close to and above its junction temperature?
As the max junction temperature is approached and exceeded, what is the effect on the output voltage.
Is it possible for the part to become unstable…
Please find the attachment missing in the last email.
I used adf4360-0 to synthesize a 2.5GHz clock, but the clock can not lock. the schematic, ADISimPLL simulation file and register configuration values are attached.
The 3-wire interface is controlled by a FPGA, and the interval between the control latch…