I've attached the artwork, BOM, assy and fab drawing for the HMC988.
The HMC988 requires a 3.3V rail to power SPI communications. The HMC988 eval board was designed to make use of the internal 3.3V LDO. If you turn off the LDO you lose the 3.3V rail and will not be able to communicate with the part.
Hello, I need to drive a 4 GHz clock from one HMC987 to four HMC988 running in parallel. Each HMC988 then outputs a 1 GHz clock signal.
Question: How can I trigger the four HMC988 to be phase aligned?
Also, how should I write to the SPI buses from a laptop…
You require external 10K pullups or pulldowns on the HMC988 to set the chip select address. No internal pullup/down resistors were added on the Chip0, 1, 2 pins.
You can connect the HMC988 with HMC1035 to the same SPI bus. Just set the HMC988 to anything…
The HMC988 is the only clock distribution device in the ADI portfolio which will run to 5V.
I have a requirement where I'd like to use the HMC988. My requirement will require for me to modify an input clock via a Divide-By factor to produce a new output clock.
For my clocking requirement, the output clock must maintain a 50% duty…
I found my the answer I was looking for in the datasheet. In Table 12, the description for "RX Buffer DC Bias Select" states: "Use 1 for sinusoidal / non-LVPECL AC coupled inputs".
In addition, another thread titled "Sine wave input…
I have an application where I need the output stage of an HMC988 to not drive until enabled. From the datasheet, the LVPECL output is enabled by default on power-on reset (Reg 01h). However, from figure 5 (SYNC/SLIP Circuit Diagram) it appears that…
In the HMC988 datasheet page 17, "HMC988LP3E Input Stage" it states
The DC bias level of 2.0 V can be generated internally byprogramming Reg04h = 1, supplied externally, or generated via an LVPECL termination network inside the part.When…
I'd like to know what asec/√Hz is. We can see the unit in Table1 Jitter density on HMC988LP3E Data Sheet.