The HMC870, and HMC871 data sheets recommended a power sequence that conflicts with the Absolute Max Spec Table.The HMC870 and HMC871 both recommended a power up sequence as follows:
1). Set Vgg -2v;
2). Set Vctl +1;
3). Set Vdd +5.
We would like to use the HMC871 driver chip using a CML flop like a NB7V52. Is this feasible? Do you have any interface suggestions or alternatives for driving it to optimize performance?
What is the VC pin voltage to output amplitude scaling ? Is there a curve available ?
We are trying to drive an 50ohm load with a 2.5Vpp pulse at a 12MHz data rate. We need very fast edges even though the datarate is slow.
Here is the input signal into the amplifier. We are using 40GHz BW ATC coupling caps. This bias current is 81mA.