• HMC832

    Hi,

    I'm using the HMC832 in the conditions fixed in the datasheet p34 figure 52 (loop filter design).

    We choose the loop filter type 1 in the table12. The Fxtal is 40Mhz.

    I succeed in programming the module correctly and it is always locked.

    But…

  • RE: HMC832

    Hi,

    Can you help me about my problem  ?

    Do you know why the output frequency is shifted when I program 40Mhz or 80 Mhz or 160Mhz ?

    Thanks.

    Regards

    Christine

  • HMC832 : Frequency tolerance corresponding to lock detect signal

    I wanted to know:

    1. What is the frequency tolerance figure when lock detect signal goes high (upon tuning the PLL to a new frequency)? That is, within how offset has frequency settled, at the instant lock detect is driven high?

    2. How the lock detect…

  • RE: HMC832 Frequency hopping method...

    Marked as answered due to lack of reply

  • RE: Signal Behavior on HMC832 VTUNE Pin

    Thank you very much. Your answer helped increase my understanding further, on the HMC832 functioning. With reference to your answer, I would like to know that can auto-calibration time be as large as to be in order of tens of milli-seconds? In the second…

  • HMC832 frequency lock by loading the GUI generated register file

    Hi,

    I am working on the HMC832 and I want to verify the frequency locking mechanism by loading the register file from the GUI using the EVAL board. 

    The HMC832 is set to Fout=735MHz, using a 26MHz reference and RDiv=1, operating in integer mode (freq integer…

  • HMC832 MODE CHOOSING

    Hi EZ experts,

    We are designing a frequency-hopping LO.

    The LO adopt AD9914(cover 30 to 900MHz) & HMC832(cover 900MHz to 3000MHz, and be AD9914's system CLK)

    The Loop filter has been desired to use type 2

    We saw  [Exact Frequency Mode] and [Exact…

  • RE: HMC832

    Hi,

    Unfortunately, I cannot provide cad file. PDF schematic, gerber files and BOM can be found in the link below. 

    https://www.analog.com/en/products/hmc832.html#product-evaluationkit

    Regards,

    Kudret

  • HMC832 LD configuration with Low PFD Frequency

    I'm trying to get the PFD frequency to 500kHz in integer mode.

    I calculated the LD window time using Equation 11 on datasheet, and it was 1000ns.

    But In Table 9 , maximum window time that can be set is 338ns.How should I set the LD window size?

  • How to change the default states of the HMC832 registers?

    Hi!

    I tuned the chip HMC832 on EV1HMC832ALP6G evaluation PCB to the required signal frequency using the software HMC PLL Evaluation Main GUI, but the settings disappeared after the power was turned off. How to change the default states of the registers…