• HMC7044 hosted on EVAL-HMC7044

    I am planning to use an HMC7044 hosted on EVAL-HMC7044 as part of a clock distribution design to synchronize numerous ADCs.  For bench applications I have suitable input reference clocks.

    However, for initial deployed evaluation, I am looking for a smaller…

  • About HMC7044

    Hello

    Is HMC7704 compatible with JESD204C?

    I would appreciate it if you could reply.

    Best Regards,
    Knj

  • RE: HMC7044 LVDS input

    Hi Joe,

    Register settings for OSCIN buffer is set for AC coupled 100 ohm differential termination by default. You can use apply differential AC coupled LVDS signal to OSCIN as given in Setup B by disabling internal 100 ohm termination and setting Hi-…

  • HMC7044 Eval Board Phase Noise

    I have a question somewhat similar to this one: https://ez.analog.com/clock_and_timing/f/q-a/549217/hmc7044-pll-phase-noise-degradation/432153#432153

    I am trying to take phase noise measurements using the evaluation board, as-is. By that I mean I haven…

  • How to design HMC7044 loop filter?ADIsimPLL 4.1 did not include HMC7044.

    How to design HMC7044 loop filter?ADIsimPLL 4.1 did not include HMC7044.

  • RE: HMC7044 LVDS output

    Hi Joe,

    LVDS High power setting seems slightly higher than the maximum value of your FPGA but you can use low power LVDS which provides lower swing at the output. To enable/disable low/high power setting for a certain channel, you need to set/reset "High…

  • HMC7044 PLL Phase noise degradation

    Hi everyone,

    I am using HMC7044 PLL for providing sampling Clock of 1228.8MHz to ADC AD9695.  I have configured the following settings in PLL1 and PLL2

    PLL1 Configuration
    Ref Frequency : 100MHz External Clock from signal Generator
    IN0 prescaler : 100
    R1 Divider…

  • RE: HMC7044(HMC7043) spurious of finput/2

    Hi y_suzuki,

    I've checked this in the lab and I am seeing fin/2 spurious signal around ~55 dBc. The reason of the difference between you and me might be related with supply decoupling and how supplies are separated. 

    I also consulted to a colleage…

  • RE: HMC7044 PLL1 not lock

    Hi,

    Divider settings seems good. Which VCXO are you using? When I simulate your PLL1 loop filter with CVHD-950-122.88 VCXO, loop seems unstable as shown below. What is your charge pump setting for PLL1? 

    You can download the ADISIMCLK and model the VCXO…