• HMC7044 hosted on EVAL-HMC7044

    I am planning to use an HMC7044 hosted on EVAL-HMC7044 as part of a clock distribution design to synchronize numerous ADCs.  For bench applications I have suitable input reference clocks.

    However, for initial deployed evaluation, I am looking for a smaller…


    This is not quite right. 

    Providing reference clock to PLL1 of HMC7044 from FPGA will provide that internal VCO is aligned with the FPGA. 

    To provide alignment between ADC, DDS, FPGA, you need to care about the trace lengths. HMC7044 will provide the synchronization…

  • HMC7044 Configuration on ADRV9009-ZU11EG with FMCOMMS8


    We are looking to design a custom carrier board to support the ZU11EG SOM and FMCOMMS8 daughterboard and I wanted to raise a few questions about the proper configuration of the HMC7044(s)

    • It seems that the HMC7044 on the carrier board is required…
  • RE: HMC7044 Output Frequencies


    OSCIN input is the reference input for PLL2, not CLKINx inputs. 

    PLL1 is used to lock the VCXO on OSCIN to a system reference clock provided with CLKINx. Internal VCO is locked on the VCXO on OSCIN input. Since you are not providing any clock to OSCIN…



    1- Yes, you can use 5 dBm sinewave AC coupled configuration to drive OSCIN pin.

    2- Control voltage of the part is specified from 0.3V to 3V and it is compatible with PLL1 output of HMC7044. 

    3- Block diagram seems good to configure PLL1 and PLL2. 

  • How to design HMC7044 loop filter?ADIsimPLL 4.1 did not include HMC7044.

    How to design HMC7044 loop filter?ADIsimPLL 4.1 did not include HMC7044.

  • RE: HMC7044 PLL1 unlock


    Are they updating the OSCIN prescaler value? The clocks entering the REF MUX&LOS block should have same or at least close frequencies. 

    If they are not updating the OSCIN prescaler, output of OSCIN prescaler is 30.72 while output of R0 Prescaler…

  • HMC7044使用


  • RE: How to enable debugfs for HMC7044 for iio_reg

    This is all working now. To get this working I had to do the following:

    1) Upgrade to 2019_R2 release of the ADI kernel.

    2) The Xilinx Zynq PS SPI master doesn't support three wire mode so I had to add some firmware to the PL to be able to control the…

  • HMC7044-CLKIN pin specification-Reg

    Hi everyone,

    I am using HMC7044 PLL with single ended CLKIN input of 25MHz frequency from LVCMOS 3.3 level.

    In datasheet, I saw the single ended connections with 3.3 Driver through a 47 ohm series resistor in Figure 29.

    But in specifications table, it…