• RE: Cascading Multiple HMC7043

    Hello Mikael,

    Firstly, what you are trying to do is completely possible and correct in general.

    Let me call:
    - the source HMC7043 as HMC7043-0
    - other parts (second level) as HMC7043-1
    - the external synchronization signal to HMC7043-0 as RFSYNC-0
    - the…

  • Can HMC7043 correctly work with RFSYNCIN synchronization frequency value at 1440[kHz]?

    Dear Experts,

    My customer wants to ask you about the following question in HMC7043. Could you please reply to the following question?

    Q1: Can HMC7043 work with the following clock frequency values correctly?

    1) CLKIN frequency range: 200[MHz] to 3200…

  • hmc7044 and hmc7043 clock tree question

    I read a technical article about "Synchronizing Sample Clocks of  a  Data Converter Array", and have the same architecture。HMC7044 CLKOUT is the CLKIN of the hmc7043,HMC7044 SCLKOUT is the RFSYNC of the HMC7043;

    the hmc7044 VCO frequency is 2…

  • RE: Synchronization of Multiple AD9959


    The min input frequency for HMC7043 is 200MHz. If a valid input signal is not applied then a noise-wise signal may be generated. In other words HMC7043 cannot be used to buffer pulsed signals. If the SYNC_OUT signal is a continuous well-defined signal…

  • RE: HMC7043 synchronization

    Thanks a lot! What about the input clock of the HMC7043. should input clocks (3 GHz) of multiple HMC7043 have the same phases or can be different? If they have different phases will all outputs of multiple HMC7043 be in phase after simultaneous arrival…

  • HMC7043 Thermal resistance values (Theta-JC/JA)?

    Dear Experts,

    My customer wants to know the following thermal resistance values of HMC7043. Could you please advise my customer about those values?


    Q1: Thermal resistance (Theta-JC) from the Junction to the Case in HMC7043.

    Q2: Thermal resistance…

  • RE: HMC7043 Power supply regulator design with HMC7043 EVM board.

    Hello Kazim-san, thank you so much for your kind reply.

    I am so sorry to ask you about the following questions again.

    Q3: I reviewed the HMC7043 EVM board circuit schematics again and then found my misunderstanding as shown below.

    The LT1963 output…

  • HMC7043 Sysref Timer Enable Question

    We are using HMC7043 devices in a cascaded structure (lead HMC7043 device followed by two other secondary HMC7043 devices in parallel with one another).  At startup, we align the divider phases.  We then initialize our other devices that are downstream…

  • HMC7044 and HMC7043

    I am driving 10 output clocks from the HMC7044 and 10 output clocks from the HMC7043. One of the outputs from the HMC7044 is the Input clock for the HMC7043. Can all the clocks be synchronous?

    I have read several documents about having a HMC7044 drive…

  • RE: The synchronization and output swing problems of HMC7043

    Hi Kazim,

    Thanks very much for your timely replay.


    (1)  I don’t use the HMC7043 evaluation board. The board is designed by myself, and I configure HMC7043 through FPGA, The attached is the list that we configured HMC7043.By the way, I resync HMC7043…