When the sysref pulse is generated, the feedback from the register shows that the clock output phase is unstable, but the oscilloscope can catch the clock pulse, is this normal?

Hi there,

I have browsed other posts and used the GPO pin to check the "clock ouputs phase status", while there is a problem.

The 0x0046 is programmed by 0x00 and 0x0050 is programmed by 0x0F, the GPO status received by FPGA is always high.That…

While we use the single HMC7043 to generate DCLK and SYSREF,when we are at 55 degrees Celsius,We found that sometimes when power on star up,SYSREF will not boot to boot.

The previous post we asked was

 HMC7043 output sysref phase difference 

We write down…

We use the single HMC7043 to generate DCLK and SYSREF,when we are at -40 degrees Celsius,We found that sometimes when power on star up,SYSREF will not  boot to boot.

Our clock frequency is 245.76MHz, and the sysref frequency is 960kHz .When sysref not…

Hi,

    We have designed a board with two level HMC7043 tree, the structure is as the following figure.

  ALL 7043 is set to single pulse mode. The input of RFSYNC of all Chips is single pulse with dc couple.  Afiter init all the 7043, we can trigger the…

我一直遇到以下问题，就是多颗HMC7043芯片的同步问题。希望你能帮忙解答一下：
HMC7043 的 RFSYNC 信号是一个脉冲而且相位完全相同。RFSYNC和CLKIN 信号由评估板提供。然而，由触发的两个下级HMC7043产生的 SYSREF 信号具有不固定的相位差，在 5ns 和 200ns 之间。

0x0091 是 0x02，SYSREF 的波形看起来是正确的。配置文件如下。
我怎么做能让相位差固定在一个值？，